Neural network accelerators with low latency and low energy consumption are desirable for edge computing. To create such accelerators, we propose a design flow for accelerating the extremely low bit-width neural network (ELB-NN) in embedded FPGAs with hybrid quantization schemes. This flow covers both network training and FPGA-based network deployment, which facilitates the design space exploration and simplifies the tradeoff between network accuracy and computation efficiency. Using this flow helps hardware designers to deliver a network accelerator in edge devices under strict resource and power constraints. We present the proposed flow by supporting hybrid ELB settings within a neural network. Results show that our design can deliver very high performance peaking at 10.3 TOPS and classify up to 325.3 image/s/watt while running large-scale neural networks for less than 5W using embedded FPGA. To the best of our knowledge, it is the most energy efficient solution in comparison to GPU or other FPGA implementations reported so far in the literature.

在嵌入式FPGA中，通过混合量化方案加速极低比特宽度神经网络（ELB-NN），提出了一种设计流程，既涵盖了网络的训练，也包含了基于FPGA的网络部署，从而方便设计者探索设计空间，简化网络精度和计算效率之间的权衡，巧妙地在资源和功耗限制条件下提供边缘设备中的网络加速器，实现高达10.3 TOPS的高性能，每瓦分类达到325.3张图像。在文献中，我们比较了GPU或其他FPGA实现，结果显示出目前最省能的解决方案。

在嵌入式FPGA中加速混合极低位宽神经网络的设计流程