This paper introduces a novel optimization framework for deep neural network (DNN) hardware accelerators, enabling the rapid development of customized and automated design flows. More specifically, our approach aims to automate the selection and configuration of low-level optimization techniques, encompassing DNN and FPGA low-level optimizations. We introduce novel optimization and transformation tasks for building design-flow architectures, which are highly customizable and flexible, thereby enhancing the performance and efficiency of DNN accelerators. Our results demonstrate considerable reductions of up to 92\% in DSP usage and 89\% in LUT usage for two networks, while maintaining accuracy and eliminating the need for human effort or domain expertise. In comparison to state-of-the-art approaches, our design achieves higher accuracy and utilizes three times fewer DSP resources, underscoring the advantages of our proposed framework.

本论文介绍了一种新的针对深度神经网络（DNN）硬件加速器的优化框架，它能够快速开发定制化和自动化的设计流程，同时具有高度可定制性和灵活性，通过引入新的优化和转换任务，不需要人类专业知识，可以在保持准确性的同时大幅度降低DSP和LUT使用，相较于现有技术，具有更高的精度和更少的DSP资源使用率。

MetaML：用于深度学习加速的可定制跨阶段设计流程自动化