Field-programmable gate arrays (FPGAs) are widely used to implement deep learning inference. Standard deep neural network inference involves the computation of interleaved linear maps and nonlinear activation functions. Prior work for ultra-low latency implementations has hardcoded the combination of linear maps and nonlinear activations inside FPGA lookup tables (LUTs). Our work is motivated by the idea that the LUTs in an FPGA can be used to implement a much greater variety of functions than this. In this paper, we propose a novel approach to training neural networks for FPGA deployment using multivariate polynomials as the basic building block. Our method takes advantage of the flexibility offered by the soft logic, hiding the polynomial evaluation inside the LUTs with zero overhead. We show that by using polynomial building blocks, we can achieve the same accuracy using considerably fewer layers of soft logic than by using linear functions, leading to significant latency and area improvements. We demonstrate the effectiveness of this approach in three tasks: network intrusion detection, jet identification at the CERN Large Hadron Collider, and handwritten digit recognition using the MNIST dataset.

使用多元多项式作为基本构建模块，我们提出了一种新的方法，通过软逻辑将多项式计算隐藏在LUTs内部，从而在FPGA部署上训练神经网络，实现相同的准确性，同时显著降低延迟和面积。我们在网络入侵检测、CERN大型强子对撞机的喷气识别和MNIST数据集的手写数字识别三个任务中展示了这种方法的有效性。

PolyLUT: 学习分段多项式用于超低延迟的FPGA基于LUT的推理