Gate sizing plays an important role in timing optimization after physical design. Existing machine learning-based gate sizing works cannot optimize timing on multiple timing paths simultaneously and neglect the physical constraint on layouts. They cause sub-optimal sizing solutions and low-efficiency issues when compared with commercial gate sizing tools. In this work, we propose a learning-driven physically-aware gate sizing framework to optimize timing performance on large-scale circuits efficiently. In our gradient descent optimization-based work, for obtaining accurate gradients, a multi-modal gate sizing-aware timing model is achieved via learning timing information on multiple timing paths and physical information on multiple-scaled layouts jointly. Then, gradient generation based on the sizing-oriented estimator and adaptive back-propagation are developed to update gate sizes. Our results demonstrate that our work achieves higher timing performance improvements in a faster way compared with the commercial gate sizing tool.

我们提出了一种基于学习驱动的物理感知门尺寸调整框架，以有效地在大规模电路上优化时序性能。通过在多个时序路径上学习时序信息和多个尺寸布局上学习物理信息，我们的研究实现了多模态门尺寸感知时序模型，并通过梯度下降优化和自适应反向传播更新门尺寸，取得了与商业门尺寸工具相比更高的时序性能改善和更快的速度。

学习驱动的物理感知大规模电路门尺寸调整