Pixel Processor Arrays (PPA) present a new vision sensor/processor architecture consisting of a SIMD array of processor elements, each capable of light capture, storage, processing and local communication. Such a device allows visual data to be efficiently stored and manipulated directly upon the focal plane, but also demands the invention of new approaches and algorithms, suitable for the massively-parallel fine-grain processor arrays. In this paper we demonstrate how various image transformations, including shearing, rotation and scaling, can be performed directly upon a PPA. The implementation details are presented using the SCAMP-5 vision chip, that contains a 256x256 pixel-parallel array. Our approaches for performing the image transformations efficiently exploit the parallel computation in a cellular processor array, minimizing the number of SIMD instructions required. These fundamental image transformations are vital building blocks for many visual tasks. This paper aims to serve as a reference for future PPA research while demonstrating the flexibility of PPA architectures.

像素处理器阵列（PPA）是一种新的视觉传感器/处理器架构，具有一组SIMD处理元素，每个元素能够进行光捕获、存储、处理和本地通信。本文展示了如何直接在PPA上执行各种图像变换，包括错切、旋转和缩放。通过在蜂窝处理器阵列中利用并行计算，以最小化所需的SIMD指令数量，有效地执行了图像变换。这些基本图像变换是许多视觉任务的重要构建模块，同时本文旨在作为未来PPA研究的参考，并展示了PPA架构的灵活性。

将图像变换映射到像素处理器阵列