Automatically designing fast and space-efficient digital circuits is challenging because circuits are discrete, must exactly implement the desired logic, and are costly to simulate. We address these challenges with CircuitVAE, a search algorithm that embeds computation graphs in a continuous space and optimizes a learned surrogate of physical simulation by gradient descent. By carefully controlling overfitting of the simulation surrogate and ensuring diverse exploration, our algorithm is highly sample-efficient, yet gracefully scales to large problem instances and high sample budgets. We test CircuitVAE by designing binary adders across a large range of sizes, IO timing constraints, and sample budgets. Our method excels at designing large circuits, where other algorithms struggle: compared to reinforcement learning and genetic algorithms, CircuitVAE typically finds 64-bit adders which are smaller and faster using less than half the sample budget. We also find CircuitVAE can design state-of-the-art adders in a real-world chip, demonstrating that our method can outperform commercial tools in a realistic setting.

自动设计快速且节省空间的数字电路是具有挑战性的，本文介绍了CircuitVAE算法，该算法通过将计算图嵌入到连续空间中并通过梯度下降优化学习到的仿真模拟来应对这些挑战，我们的算法具有高样本效率，能够优化大型问题实例并适应高样本预算，测试结果表明CircuitVAE在设计大型电路方面表现出色，并能在真实芯片中设计出最先进的加法器，证明了我们的方法在实际环境中能够胜过商业工具。

CircuitVAE：高效且可扩展的潜在电路优化