Uncertainty estimation is an indispensable capability for AI-enabled, safety-critical applications, e.g. autonomous vehicles or medical diagnosis. Bayesian neural networks (BNNs) use Bayesian statistics to provide both classification predictions and uncertainty estimation, but they suffer from high computational overhead associated with random number generation and repeated sample iterations. Furthermore, BNNs are not immediately amenable to acceleration through compute-in-memory architectures due to the frequent memory writes necessary after each RNG operation. To address these challenges, we present an ASIC that integrates 360 fJ/Sample Gaussian RNG directly into the SRAM memory words. This integration reduces RNG overhead and enables fully-parallel compute-in-memory operations for BNNs. The prototype chip achieves 5.12 GSa/s RNG throughput and 102 GOp/s neural network throughput while occupying 0.45 mm2, bringing AI uncertainty estimation to edge computation.

本研究解决了贝叶斯神经网络在进行不确定性估计时的高计算开销问题，特别是在随机数生成和多次样本迭代方面。提出了一种将360 fJ/样本的高斯随机数生成器直接集成到SRAM内存字中的硬件加速解决方案，从而降低了计算开销并实现了全并行的内存计算操作。该原型芯片在边缘计算中实现了5.12 GSa/s的随机数生成吞吐量和102 GOp/s的神经网络吞吐量，显著提升了人工智能的不确定性估计能力。

一个65纳米的贝叶斯神经网络加速器，具有360 fJ/样本的内存中高斯随机数生成器，用于人工智能的不确定性估计