Logic synthesis, a pivotal stage in chip design, entails optimizing chip
specifications encoded in hardware description languages like Verilog into
highly efficient implementations using Boolean logic gates. The process
involves a sequential application of logic minimization heuristics (``synthesis
recipe"), with their arrangement significantly impacting crucial metrics such
as area and delay. Addressing the challenge posed by the broad spectrum of
design complexities - from variations of past designs (e.g., adders and
multipliers) to entirely novel configurations (e.g., innovative processor
instructions) - requires a nuanced `synthesis recipe` guided by human expertise
and intuition. This study conducts a thorough examination of learning and
search techniques for logic synthesis, unearthing a surprising revelation:
pre-trained agents, when confronted with entirely novel designs, may veer off
course, detrimentally affecting the search trajectory. We present ABC-RL, a
meticulously tuned $\alpha$ parameter that adeptly adjusts recommendations from
pre-trained agents during the search process. Computed based on similarity
scores through nearest neighbor retrieval from the training dataset, ABC-RL
yields superior synthesis recipes tailored for a wide array of hardware
designs. Our findings showcase substantial enhancements in the
Quality-of-result (QoR) of synthesized circuits, boasting improvements of up to
24.8% compared to state-of-the-art techniques. Furthermore, ABC-RL achieves an
impressive up to 9x reduction in runtime (iso-QoR) when compared to current
state-of-the-art methodologies.

本研究对逻辑综合的学习和搜索技术进行了彻底的研究，发现预训练代理器在面对全新设计时可能偏离轨道，从而对搜索轨迹产生不利影响。我们提出了 ABC-RL，这是一个经过精心调整的 α 参数，能够在搜索过程中熟练地调整来自预训练代理器的建议。基于与训练数据集的最近邻检索相似性分数计算得到的 ABC-RL 针对广泛的硬件设计提供了优越的综合方案。我们的发现展示了合成电路质量结果（QoR）的显著改进，与现有技术相比，提高了最高达 24.8% 的性能。此外，与当前最先进的方法相比，ABC-RL 在运行时间上实现了高达 9 倍的减少（iso-QoR）。