Modern machine learning (ML) applications are becoming increasingly complex
and monolithic (single chip) accelerator architectures cannot keep up with
their energy efficiency and throughput demands. Even though modern digital
electronic accelerators are gradually adopting 2.5D architectures with multiple
smaller chiplets to improve scalability, they face fundamental limitations due
to a reliance on slow metallic interconnects. This paper outlines how optical
communication and computation can be leveraged in 2.5D platforms to realize
energy-efficient and high throughput 2.5D ML accelerator architectures.

现代机器学习应用越来越复杂，单芯片加速器架构无法满足其能效和吞吐量要求。本文介绍了如何利用光通信和计算在 2.5D 平台上实现能效高、吞吐量大的 2.5D 机器学习加速器架构。

克服规模扩展机器学习硬件加速器中的通信瓶颈的硅光 2.5D 互联网

Silicon Photonic 2.5D Interposer Networks for Overcoming Communication  Bottlenecks in Scale-out Machine Learning Hardware Accelerators

Convolutional neural networks have shown tremendous performance capabilities
in computer vision tasks, but their excessive amounts of weight storage and
arithmetic operations prevent them from being adopted in embedded environments.
One of the solutions involves pruning, where certain unimportant weights are
forced to have a value of zero. Many pruning schemes have been proposed, but
these have mainly focused on the number of pruned weights. Previous pruning
schemes scarcely considered ASIC or FPGA accelerator architectures. When these
pruned networks are run on accelerators, the lack of consideration of the
architecture causes some inefficiency problems, including internal buffer
misalignments and load imbalances. This paper proposes a new pruning scheme
that reflects accelerator architectures. In the proposed scheme, pruning is
performed so that the same number of weights remain for each weight group
corresponding to activations fetched simultaneously. In this way, the pruning
scheme resolves the inefficiency problems, doubling the accelerator
performance. Even with this constraint, the proposed pruning scheme reached a
pruning ratio similar to that of previous unconstrained pruning schemes, not
only on AlexNet and VGG16 but also on state-of-the-art very deep networks such
as ResNet. Furthermore, the proposed scheme demonstrated a comparable pruning
ratio on compact networks such as MobileNet and on slimmed networks that were
already pruned in a channel-wise manner. In addition to improving the
efficiency of previous sparse accelerators, it will be also shown that the
proposed pruning scheme can be used to reduce the logic complexity of sparse
accelerators.The pruned models are publicly available at
this https URL

在嵌入式环境中，卷积神经网络因其过多的权重存储和算术运算而未能得到广泛应用，为解决这一问题，本文提出了一种新的修剪方案，以反映加速器架构，通过此方案，性能得到了大幅提升，并成功应用于 AlexNet，VGG16，ResNet，MobileNet 等多种网络模型。