Today's performance analysis frameworks for deep learning accelerators suffer
from two significant limitations. First, although modern convolutional neural
network (CNNs) consist of many types of layers other than convolution,
especially during training, these frameworks largely focus on convolution
layers only. Second, these frameworks are generally targeted towards inference,
and lack support for training operations. This work proposes a novel
performance analysis framework, SimDIT, for general ASIC-based systolic
hardware accelerator platforms. The modeling effort of SimDIT comprehensively
covers convolution and non-convolution operations of both CNN inference and
training on a highly parameterizable hardware substrate. SimDIT is integrated
with a backend silicon implementation flow and provides detailed end-to-end
performance statistics (i.e., data access cost, cycle counts, energy, and
power) for executing CNN inference and training workloads. SimDIT-enabled
performance analysis reveals that on a 64X64 processing array, non-convolution
operations constitute 59.5% of total runtime for ResNet-50 training workload.
In addition, by optimally distributing available off-chip DRAM bandwidth and
on-chip SRAM resources, SimDIT achieves 18X performance improvement over a
generic static resource allocation for ResNet-50 inference.

本文提出了一种针对深度学习加速器的性能分析框架 ——SimDIT，旨在覆盖卷积和非卷积操作，并提供详细的执行 CNN 推断和训练工作量的端到端性能统计，结果显示，在使用一个 64X64 处理阵列时，ResNet-50 训练工作量的非卷积操作占总运行时间的 59.5％。此外，通过优化可用的片外 DRAM 带宽和片上 SRAM 资源的分配，SimDIT 实现了比 ResNet-50 推理的通用静态资源分配高出 18 倍的性能提升。