Driveable area detection is a key component for various applications in the
field of autonomous driving (AD), such as ground-plane detection, obstacle
detection and maneuver planning. Additionally, bulky and over-parameterized
networks can be easily forgone and replaced with smaller networks for faster
inference on embedded systems. The driveable area detection, posed as a two
class segmentation task, can be efficiently modeled with slim binary networks.
This paper proposes a novel binarized driveable area detection network (binary
DAD-Net), which uses only binary weights and activations in the encoder, the
bottleneck, and the decoder part. The latent space of the bottleneck is
efficiently increased (x32 -> x16 downsampling) through binary dilated
convolutions, learning more complex features. Along with automatically
generated training data, the binary DAD-Net outperforms state-of-the-art
semantic segmentation networks on public datasets. In comparison to a
full-precision model, our approach has a x14.3 reduced compute complexity on an
FPGA and it requires only 0.9MB memory resources. Therefore, commodity
SIMD-based AD-hardware is capable of accelerating the binary DAD-Net.

本研究提出了一种新的二元化驾驶区域检测网络（Binary DAD-Net），可用于自动驾驶汽车中的障碍物检测和操作规划，具有高效的模型和自动生成的数据集，且相比精确模型，在 FPGA 上计算复杂度降低了 14.3 倍，仅需要 0.9MB 内存资源。