Approximate computing is an emerging paradigm where design accuracy can be
traded off for benefits in design metrics such as design area, power
consumption or circuit complexity. In this work, we present a novel paradigm to
synthesize approximate circuits using Boolean matrix factorization (BMF). In
our methodology the truth table of a sub-circuit of the design is approximated
using BMF to a controllable approximation degree, and the results of the
factorization are used to synthesize a less complex subcircuit. To scale our
technique to large circuits, we devise a circuit decomposition method and a
subcircuit design-space exploration technique to identify the best order for
subcircuit approximations. Our method leads to a smooth trade-off between
accuracy and full circuit complexity as measured by design area and power
consumption. Using an industrial strength design flow, we extensively evaluate
our methodology on a number of testcases, where we demonstrate that the
proposed methodology can achieve up to 63% in power savings, while introducing
an average relative error of 5%. We also compare our work to previous works in
Boolean circuit synthesis and demonstrate significant improvements in design
metrics for same accuracy targets.

该论文提出了一种新的用于综合近似电路的技术，采用布尔矩阵分解对电路子电路的真值表进行逼近，以获取更低复杂度的子电路，实验表明此方法可在不影响准确度的情况下，节约高达 63% 的功耗。