Error Detection and Correction Codes (ECCs) are often used in digital designs
to protect data integrity. Especially in safety-critical systems such as
automotive electronics, ECCs are widely used and the verification of such
complex logic becomes more critical considering the ISO 26262 safety standards.
Exhaustive verification of ECC using formal methods has been a challenge given
the high number of data bits to protect. As an example, for an ECC of 128 data
bits with a possibility to detect up to four-bit errors, the combination of bit
errors is given by 128C1 + 128C2 + 128C3 + 128C4 = 1.1 * 10^7. This vast
analysis space often leads to bounded proof results. Moreover, the complexity
and state-space increase further if the ECC has sequential encoding and
decoding stages. To overcome such problems and sign-off the design with
confidence within reasonable proof time, we present a pragmatic formal
verification approach of complex ECC cores with several complexity reduction
techniques and know-how that were learnt during the course of verification. We
discuss using the linearity of the syndrome generator as a helper assertion,
using the abstract model as glue logic to compare the RTL with the sequential
version of the circuit, k-induction-based model checking and using mathematical
relations captured as properties to simplify the verification in order to get
an unbounded proof result within 24 hours of proof runtime.

复杂纠错码核心的实际形式验证方法，使用多个复杂度降低技术和专业知识，包括使用综合序列版本的电路与 RTL 进行比较的抽象模型作为粘合逻辑，基于 k 归纳的模型检查和使用数学关系作为属性捕获来简化验证，以在 24 小时内获得无界的证明结果。

用于安全关键设计中的顺序错误检测和纠错码（ECC）的实用形式验证

Pragmatic Formal Verification of Sequential Error Detection and  Correction Codes (ECCs) used in Safety-Critical Design

Deep neural networks have achieved state-of-the art performance on various
computer vision tasks. However, their deployment on resource-constrained
devices has been hindered due to their high computational and storage
complexity. While various complexity reduction techniques, such as lightweight
network architecture design and parameter quantization, have been successful in
reducing the cost of implementing these networks, these methods have often been
considered orthogonal. In reality, existing quantization techniques fail to
replicate their success on lightweight architectures such as MobileNet. To this
end, we present a novel fully differentiable non-uniform quantizer that can be
seamlessly mapped onto efficient ternary-based dot product engines. We conduct
comprehensive experiments on CIFAR-10, ImageNet, and Visual Wake Words
datasets. The proposed quantizer (DBQ) successfully tackles the daunting task
of aggressively quantizing lightweight networks such as MobileNetV1,
MobileNetV2, and ShuffleNetV2. DBQ achieves state-of-the art results with
minimal training overhead and provides the best (pareto-optimal)
accuracy-complexity trade-off.

本文提出了一种全新的可完全微分的非均匀量化器，在轻量级神经网络（如 MobileNetV1，MobileNetV2 和 ShuffleNetV2）上取得了最优的准确性 - 复杂度平衡，并成功地解决了将神经网络部署到资源受限设备上的问题。