Internet of Things (IoT) and smart wearable devices for personalized
healthcare will require storing and computing ever-increasing amounts of data.
The key requirements for these devices are ultra-low-power, high-processing
capabilities, autonomy at low cost, as well as reliability and accuracy to
enable Green AI at the edge. Artificial Intelligence (AI) models, especially
Bayesian Neural Networks (BayNNs) are resource-intensive and face challenges
with traditional computing architectures due to the memory wall problem.
Computing-in-Memory (CIM) with emerging resistive memories offers a solution by
combining memory blocks and computing units for higher efficiency and lower
power consumption. However, implementing BayNNs on CIM hardware, particularly
with spintronic technologies, presents technical challenges due to variability
and manufacturing defects. The NeuSPIN project aims to address these challenges
through full-stack hardware and software co-design, developing novel
algorithmic and circuit design approaches to enhance the performance,
energy-efficiency and robustness of BayNNs on sprintronic-based CIM platforms.

通过全栈硬件和软件共同设计，NeuSPIN 项目旨在解决基于自旋电子技术的 CIM 平台上 BayNNs 的可变性和制造缺陷所带来的挑战，并开发新的算法和电路设计方法，以提高 BayNNs 在 CIM 硬件上的性能，能效和稳健性。

NeuSpin：基于自旋电子技术的可靠边缘神经形态系统设计，用于绿色人工智能

NeuSpin: Design of a Reliable Edge Neuromorphic System Based on  Spintronics for Green AI

Architectures that incorporate Computing-in-Memory (CiM) using emerging
non-volatile memory (NVM) devices have become strong contenders for deep neural
network (DNN) acceleration due to their impressive energy efficiency. Yet, a
significant challenge arises when using these emerging devices: they can show
substantial variations during the weight-mapping process. This can severely
impact DNN accuracy if not mitigated. A widely accepted remedy for imperfect
weight mapping is the iterative write-verify approach, which involves verifying
conductance values and adjusting devices if needed. In all existing
publications, this procedure is applied to every individual device, resulting
in a significant programming time overhead. In our research, we illustrate that
only a small fraction of weights need this write-verify treatment for the
corresponding devices and the DNN accuracy can be preserved, yielding a notable
programming acceleration. Building on this, we introduce USWIM, a novel method
based on the second derivative. It leverages a single iteration of forward and
backpropagation to pinpoint the weights demanding write-verify. Through
extensive tests on diverse DNN designs and datasets, USWIM manifests up to a
10x programming acceleration against the traditional exhaustive write-verify
method, all while maintaining a similar accuracy level. Furthermore, compared
to our earlier SWIM technique, USWIM excels, showing a 7x speedup when dealing
with devices exhibiting non-uniform variations.

利用新兴的非易失性存储器设备进行计算存储的架构在深度神经网络加速中具有出色的能效，然而，这些新兴设备在权重映射过程中存在重大变化的挑战，通过我们的研究，我们引入了一种基于二阶导数的新方法 USWIM，可以加速编程达到 10 倍，同时保持类似的准确性。

U-SWIM: 通用选择性写入验证用于计算内存神经加速器

U-SWIM: Universal Selective Write-Verify for Computing-in-Memory Neural  Accelerators

Emerging non-volatile memory (NVM)-based Computing-in-Memory (CiM)
architectures show substantial promise in accelerating deep neural networks
(DNNs) due to their exceptional energy efficiency. However, NVM devices are
prone to device variations. Consequently, the actual DNN weights mapped to NVM
devices can differ considerably from their targeted values, inducing
significant performance degradation. Many existing solutions aim to optimize
average performance amidst device variations, which is a suitable strategy for
general-purpose conditions. However, the worst-case performance that is crucial
for safety-critical applications is largely overlooked in current research. In
this study, we define the problem of pinpointing the worst-case performance of
CiM DNN accelerators affected by device variations. Additionally, we introduce
a strategy to identify a specific pattern of the device value deviations in the
complex, high-dimensional value deviation space, responsible for this
worst-case outcome. Our findings reveal that even subtle device variations can
precipitate a dramatic decline in DNN accuracy, posing risks for CiM-based
platforms in supporting safety-critical applications. Notably, we observe that
prevailing techniques to bolster average DNN performance in CiM accelerators
fall short in enhancing worst-case scenarios. In light of this issue, we
propose a novel worst-case-aware training technique named A-TRICE that
efficiently combines adversarial training and noise-injection training with
right-censored Gaussian noise to improve the DNN accuracy in the worst-case
scenarios. Our experimental results demonstrate that A-TRICE improves the
worst-case accuracy under device variations by up to 33%.

对受设备变异影响的 CiM DNN 加速器的最坏情况性能进行确定，并提出一种名为 A-TRICE 的新型最坏情况感知训练技术，通过对抗训练和噪声注入训练有效地改进最坏情况下的 DNN 准确性。