The thesis investigates the utilization of memristive and memcapacitive
crossbar arrays in low-power machine learning accelerators, offering a
comprehensive co-design framework for deep neural networks (DNN). The model,
implemented through a hybrid Python and PyTorch approach, accounts for various
non-idealities, achieving exceptional training accuracies of 90.02% and 91.03%
for the CIFAR-10 dataset with memristive and memcapacitive crossbar arrays on
an 8-layer VGG network. Additionally, the thesis introduces a novel approach to
emulate meminductor devices using Operational Transconductance Amplifiers (OTA)
and capacitors, showcasing adjustable behavior. Transistor-level simulations in
180 nm CMOS technology, operating at 60 MHz, demonstrate the proposed
meminductor emulator's viability with a power consumption of 0.337 mW. The
design is further validated in neuromorphic circuits and CNN accelerators,
achieving training and testing accuracies of 91.04% and 88.82%, respectively.
Notably, the exclusive use of MOS transistors ensures the feasibility of
monolithic IC fabrication. This research significantly contributes to the
exploration of advanced hardware solutions for efficient and high-performance
machine-learning applications.

本研究通过利用 memristive 和 memcapacitive 交叉阵列在低功耗机器学习加速器中的应用，提供了一个综合的深度神经网络 (DNN) 的共同设计框架；该模型采用混合 Python 和 PyTorch 方法实现，考虑了各种非理想因素，在 8 层 VGG 网络上，对 CIFAR-10 数据集分别使用 memristive 和 memcapacitive 交叉阵列，实现了卓越的训练准确率 (90.02% 和 91.03%)；此外，本文还引入了一种使用运算跨导放大器 (OTA) 和电容器模拟 meminductor 设备的新方法，展示了可调节的行为；在 60 MHz 下，180 nm CMOS 技术的晶体管级仿真表明所提出的 meminductor 模拟器具有 0.337 mW 的功耗，进一步在神经形态电路和 CNN 加速器中进行了验证，训练和测试准确率分别达到了 91.04% 和 88.82%，值得注意的是，仅使用 MOS 晶体管确保了单片 IC 制造的可行性，这项研究为探索高效和高性能的机器学习应用的先进硬件解决方案作出了重大贡献。

基于记忆元件的神经形态硬件在神经网络应用中的研究

Mem-elements based Neuromorphic Hardware for Neural Network Application

In recent years, hardware-accelerated neural networks have gained significant
attention for edge computing applications. Among various hardware options,
crossbar arrays, offer a promising avenue for efficient storage and
manipulation of neural network weights. However, the transition from trained
floating-point models to hardware-constrained analog architectures remains a
challenge. In this work, we combine a quantization technique specifically
designed for such architectures with a novel self-correcting mechanism. By
utilizing dual crossbar connections to represent both the positive and negative
parts of a single weight, we develop an algorithm to approximate a set of
multiplicative weights. These weights, along with their differences, aim to
represent the original network's weights with minimal loss in performance. We
implement the models using IBM's aihwkit and evaluate their efficacy over time.
Our results demonstrate that, when paired with an on-chip pulse generator, our
self-correcting neural network performs comparably to those trained with
analog-aware algorithms.

近年来，硬件加速神经网络在边缘计算应用中引起了重视。在各种硬件选项中，交叉阵列为神经网络权重的高效存储和操作提供了有希望的途径。然而，从经过训练的浮点模型转向硬件约束的模拟体系结构仍然是一个挑战。在这项工作中，我们将一种专为这种体系结构设计的量化技术与一种新颖的自校正机制相结合。通过利用双交叉栏连接来表示单个权重的正负部分，我们开发了一种算法来近似一组乘法权重。这些权重以及它们的差异旨在以最小的性能损失来表示原始网络的权重。我们使用 IBM 的 aihwkit 实现了这些模型，并随时间评估了它们的效力。我们的结果表明，当与芯片上的脉冲发生器配对时，我们的自校正神经网络在性能上与那些经过模拟感知算法训练的网络相当。