Processing-in-memory (PIM) has emerged as an enabler for the energy-efficient
and high-performance acceleration of deep learning (DL) workloads. Resistive
random-access memory (ReRAM) is one of the most promising technologies to
implement PIM. However, as the complexity of Deep convolutional neural networks
(DNNs) grows, we need to design a manycore architecture with multiple
ReRAM-based processing elements (PEs) on a single chip. Existing PIM-based
architectures mostly focus on computation while ignoring the role of
communication. ReRAM-based tiled manycore architectures often involve many
Processing Elements (PEs), which need to be interconnected via an efficient
on-chip communication infrastructure. Simply allocating more resources (ReRAMs)
to speed up only computation is ineffective if the communication infrastructure
cannot keep up with it. In this paper, we highlight the design principles of a
dataflow-aware PIM-enabled manycore platform tailor-made for various types of
DL workloads. We consider the design challenges with both 2.5D interposer- and
3D integration-enabled architectures.

设计原则和挑战研究了用于深度学习的数据流感知、处理器内存结合的多核平台。