Posit has been a promising alternative to the IEEE-754 floating point format
for deep learning applications due to its better trade-off between dynamic
range and accuracy. However, hardware implementation of posit arithmetic
requires further exploration, especially for the dot-product operations
dominated in deep neural networks (DNNs). It has been implemented by either the
combination of multipliers and an adder tree or cascaded fused multiply-add
units, leading to poor computational efficiency and excessive hardware
overhead. To address this issue, we propose an open-source posit dot-product
unit, namely PDPU, that facilitates resource-efficient and high-throughput
dot-product hardware implementation. PDPU not only features the fused and
mixed-precision architecture that eliminates redundant latency and hardware
resources, but also has a fine-grained 6-stage pipeline, improving
computational efficiency. A configurable PDPU generator is further developed to
meet the diverse needs of various DNNs for computational accuracy. Experimental
results evaluated under the 28nm CMOS process show that PDPU reduces area,
latency, and power by up to 43%, 64%, and 70%, respectively, compared to the
existing implementations. Hence, PDPU has great potential as the computing core
of posit-based accelerators for deep learning applications.

该研究提出了一个名为 PDPU 的开源端点积处理器单元，旨在促进资源高效和高吞吐量的端点积硬件实现，通过优化后的硬件架构和流水线设计，可以显著降低面积、延迟和功耗，具有成为基于端点积加速器的计算核心的巨大潜力。