Though many compilation and runtime systems have been developed for DNNs in
recent years, the focus has largely been on static DNNs. Dynamic DNNs, where
tensor shapes and sizes and even the set of operators used are dependent upon
the input and/or execution, are becoming common. This paper presents SoD$^2$, a
comprehensive framework for optimizing Dynamic DNNs. The basis of our approach
is a classification of common operators that form DNNs, and the use of this
classification towards a Rank and Dimension Propagation (RDP) method. This
framework statically determines the shapes of operators as known constants,
symbolic constants, or operations on these. Next, using RDP we enable a series
of optimizations, like fused code generation, execution (order) planning, and
even runtime memory allocation plan generation. By evaluating the framework on
10 emerging Dynamic DNNs and comparing it against several existing systems, we
demonstrate both reductions in execution latency and memory requirements, with
RDP-enabled key optimizations responsible for much of the gains. Our evaluation
results show that SoD$^2$ runs up to $3.9\times$ faster than these systems
while saving up to $88\%$ peak memory consumption.

SoD$^2$ 是一个用于优化动态深度神经网络的综合框架，通过分类和使用常见操作符，结合 Rank and Dimension Propagation (RDP) 方法，实现了静态确定操作符形状并进行一系列优化，从而显著减少执行延迟和内存需求。

SoD$^2$: 静态优化动态深度神经网络

SoD$^2$: Statically Optimizing Dynamic Deep Neural Network

This paper presents MicroNAS, a system designed to automatically search and
generate neural network architectures capable of classifying time series data
on resource-constrained microcontrollers (MCUs) and generating standard tf-lite
ML models. MicroNAS takes into account user-defined constraints on execution
latency and peak memory consumption on a target MCU. This approach ensures that
the resulting neural network architectures are optimised for the specific
constraints and requirements of the MCU on which they are implemented. To
achieve this, MicroNAS uses a look-up table estimation approach for accurate
execution latency calculations, with a minimum error of only 1.02ms. This
accurate latency estimation on MCUs sets it apart from other hardware-aware
neural architecture search (HW-NAS) methods that use less accurate estimation
techniques. Finally, MicroNAS delivers performance close to that of
state-of-the-art models running on desktop computers, achieving high
classification accuracies on recognised datasets (93.93% on UCI-HAR and 96.33%
on SkodaR) while running on a Cortex-M4 MCU.

MicroNAS 是一个系统，能够自动搜索和生成神经网络体系结构，用于分类时间序列数据，应用于资源受限的微控制器 (MCUs)，并生成标准 tf-lite ML 模型。