This paper discusses a simple and effective method for the summation of long
sequences of floating point numbers. The method comprises two phases: an
accumulation phase where the mantissas of the floating point numbers are added
to accumulators indexed by the exponents and a reconstruction phase where the
actual summation result is finalised. Various architectural details are given
for both FPGAs and ASICs including fusing the operation with a multiplier,
creating efficient MACs. Some results are presented for FPGAs, including a
tensor core capable of multiplying and accumulating two 4x4 matrices of
bfloat16 values every clock cycle using ~6,400 LUTs + 64 DSP48 in AMD FPGAs at
700+ MHz. The method is then extended to posits and logarithmic numbers.

该论文讨论了一种简单有效的方法，用于对长序列的浮点数进行求和。该方法包括两个阶段：累积阶段，其中浮点数的尾数添加到由指数索引的累加器中，重构阶段，将最终的求和结果完成。对于 FPGAs 和 ASICs，给出了各种体系结构细节，包括将操作与乘法器融合，创建高效的 MAC。对于 FPGAs，给出了一些结果，包括在 AMD FPGAs 上每个时钟周期能够使用～6,400 LUTs + 64 DSP48，以 700+ MHz 的速度乘法和累加两个 4x4 矩阵的 bfloat16 值的张量核心。然后将该方法扩展到 posits 和对数数。