This paper investigates the use of Large Language Models (LLMs) for
automating the generation of hardware description code, aiming to explore their
potential in supporting and enhancing the development of efficient neuromorphic
computing architectures. Building on our prior work, we employ OpenAI's
ChatGPT4 and natural language prompts to synthesize a RTL Verilog module of a
programmable recurrent spiking neural network, while also generating test
benches to assess the system's correctness. The resultant design was validated
in three case studies, the exclusive OR,the IRIS flower classification and the
MNIST hand-written digit classification, achieving accuracies of up to 96.6%.
To verify its synthesizability and implementability, the design was prototyped
on a field-programmable gate array and implemented on SkyWater 130 nm
technology by using an open-source electronic design automation flow.
Additionally, we have submitted it to Tiny Tapeout 6 chip fabrication program
to further evaluate the system on-chip performance in the future.

探索使用大型语言模型（LLMs）自动生成硬件描述代码的潜力，以支持和增强高效的神经形态计算架构的开发，并通过三个案例研究验证其可行性和实施性。

大型语言模型和 ChatGPT 的循环脉冲神经网络的 Verilog 设计

Natural Language to Verilog: Design of a Recurrent Spiking Neural  Network using Large Language Models and ChatGPT

In the realm of ASIC engineering, the landscape has been significantly
reshaped by the rapid development of LLM, paralleled by an increase in the
complexity of modern digital circuits. This complexity has escalated the
requirements for HDL coding, necessitating a higher degree of precision and
sophistication. However, challenges have been faced due to the
less-than-optimal performance of modern language models in generating hardware
description code, a situation further exacerbated by the scarcity of the
corresponding high-quality code datasets. These challenges have highlighted the
gap between the potential of LLMs to revolutionize digital circuit design and
their current capabilities in accurately interpreting and implementing hardware
specifications. To address these challenges, a strategy focusing on the
fine-tuning of the leading-edge nature language model and the reshuffling of
the HDL code dataset has been developed. The fine-tuning aims to enhance
models' proficiency in generating precise and efficient ASIC design, while the
dataset reshuffling is intended to broaden the scope and improve the quality of
training material. The model demonstrated significant improvements compared to
the base model, with approximately 10% to 20% increase in accuracy across a
wide range of temperature for the pass@1 metric. This approach is expected to
facilitate a simplified and more efficient LLM-assisted framework for complex
circuit design, leveraging their capabilities to meet the sophisticated demands
of HDL coding and thus streamlining the ASIC development process.

通过优化 LLM 的核心自然语言模型和重新组织 HDL 代码数据集，提高生成精确且高效 ASIC 设计的模型能力，从而简化和加速复杂电路设计的 LLM 辅助框架，以满足 HDL 编码的复杂需求并优化 ASIC 开发流程。