There is an increasing need to bring machine learning to a wide diversity of
hardware devices. Current frameworks rely on vendor-specific operator libraries
and optimize for a narrow range of server-class GPUs. Deploying workloads to
new platforms -- such as mobile phones, embedded devices, and accelerators
(e.g., FPGAs, ASICs) -- requires significant manual effort. We propose TVM, a
compiler that exposes graph-level and operator-level optimizations to provide
performance portability to deep learning workloads across diverse hardware
back-ends. TVM solves optimization challenges specific to deep learning, such
as high-level operator fusion, mapping to arbitrary hardware primitives, and
memory latency hiding. It also automates optimization of low-level programs to
hardware characteristics by employing a novel, learning-based cost modeling
method for rapid exploration of code optimizations. Experimental results show
that TVM delivers performance across hardware back-ends that are competitive
with state-of-the-art, hand-tuned libraries for low-power CPU, mobile GPU, and
server-class GPUs. We also demonstrate TVM's ability to target new accelerator
back-ends, such as the FPGA-based generic deep learning accelerator. The system
is open sourced and in production use inside several major companies.

TVM 是一个深度学习编译器，可将深度学习工作负载在各种硬件后端上具有良好的性能移植性，通过学习基于成本模型的方法，自动进行低级程序的硬件特征优化，实验结果表明，TVM 在处理低功率 CPU、移动 GPU 和服务器级 GPU 的竞争性能与手工调优库类似，并能定位到新的加速器后端，如基于 FPGA 的深度学习通用加速器。