An accurate prediction of scheduling and execution of instruction streams is
a necessary prerequisite for predicting the in-core performance behavior of
throughput-bound loop kernels on out-of-order processor architectures. Such
predictions are an indispensable component of analytical performance models,
such as the Roofline and the Execution-Cache-Memory (ECM) model, and allow a
deep understanding of the performance-relevant interactions between hardware
architecture and loop code. We present the Open Source Architecture Code
Analyzer (OSACA), a static analysis tool for predicting the execution time of
sequential loops comprising x86 instructions under the assumption of an
infinite first-level cache and perfect out-of-order scheduling. We show the
process of building a machine model from available documentation and
semi-automatic benchmarking, and carry it out for the latest Intel Skylake and
AMD Zen micro-architectures. To validate the constructed models, we apply them
to several assembly kernels and compare runtime predictions with actual
measurements. Finally we give an outlook on how the method may be generalized
to new architectures.

本文介绍了一种基于静态分析的方法来建立微架构模型以预测 loop kernels 的性能，并介绍了一个名为 OSACA 的工具来建立针对 Intel Skylake 和 AMD Zen 的机器模型，并通过多个汇编内核的运行时预测和实际测量结果进行验证。

针对 Intel 和 AMD 微架构的自动化指令流吞吐量预测

Automated Instruction Stream Throughput Prediction for Intel and AMD  Microarchitectures

This paper introduces a combinatorial optimization approach to register
allocation and instruction scheduling, two central compiler problems.
Combinatorial optimization has the potential to solve these problems optimally
and to exploit processor-specific features readily. Our approach is the first
to leverage this potential in practice: it captures the complete set of program
transformations used in state-of-the-art compilers, scales to medium-sized
functions of up to 1000 instructions, and generates executable code. This level
of practicality is reached by using constraint programming, a particularly
suitable combinatorial optimization technique. Unison, the implementation of
our approach, is open source, used in industry, and integrated with the LLVM
toolchain.
An extensive evaluation confirms that Unison generates better code than LLVM
while scaling to medium-sized functions. The evaluation uses systematically
selected benchmarks from MediaBench and SPEC CPU2006 and different processor
architectures (Hexagon, ARM, MIPS). Mean estimated speedup ranges from 1.1% to
10% and mean code size reduction ranges from 1.3% to 3.8% for the different
architectures. A significant part of this improvement is due to the integrated
nature of the approach. Executing the generated code on Hexagon confirms that
the estimated speedup results in actual speedup. Given a fixed time limit,
Unison solves optimally functions of up to 946 instructions, nearly an order of
magnitude larger than previous approaches.
The results show that our combinatorial approach can be applied in practice
to trade compilation time for code quality beyond the usual compiler
optimization levels, identify improvement opportunities in heuristic
algorithms, and fully exploit processor-specific features.

本文介绍了一种基于组合优化的方法来解决编译器中两个中心问题 —— 寄存器分配和指令调度，使用约束编程技术可以达到可行且可扩展的程度，得出的实现表明其比 LLVM 生成的代码更优，能够有效地利用处理器特征，能够实现程序规模的增强。