Testing an integrated circuit (IC) is a highly compute-intensive process. For
today's complex designs, tests for many hard-to-detect faults are typically
generated using deterministic test generation (DTG) algorithms. Machine
Learning (ML) is being increasingly used to increase the test coverage and
decrease the overall testing time. Such proposals primarily reduce the wasted
work in the classic Path Oriented Decision Making (PODEM) algorithm without
compromising on the test quality. With variants of PODEM, many times there is a
need to backtrack because further progress cannot be made. There is thus a need
to predict the best strategy at different points in the execution of the
algorithm. The novel contribution of this paper is a 2-level predictor: the top
level is a meta predictor that chooses one of several predictors at the lower
level. We choose the best predictor given a circuit and a target net. The
accuracy of the top-level meta predictor was found to be 99\%. This leads to a
significantly reduced number of backtracking decisions compared to
state-of-the-art ML-based and conventional solutions. As compared to a popular,
state-of-the-art commercial ATPG tool, our 2-level predictor (HybMT) shows an
overall reduction of 32.6\% in the CPU time without compromising on the fault
coverage for the EPFL benchmark circuits. HybMT also shows a speedup of 24.4\%
and 95.5\% over the existing state-of-the-art (the baseline) while obtaining
equal or better fault coverage for the ISCAS'85 and EPFL benchmark circuits,
respectively.

本文提出了一种基于机器学习的、优化整合电路测试的算法，通过使用分层和元预测器，相较于现有的商业软件和基线算法，能够在保证测试质量的前提下，将 CPU 时间减少 32.6%，测试进度加快 24.4% 到 95.5%。

HybMT: 基于混合元预测器的机器学习算法用于快速测试向量生成

HybMT: Hybrid Meta-Predictor based ML Algorithm for Fast Test Vector  Generation

The globalization of the Integrated Circuit (IC) supply chain has moved most
of the design, fabrication, and testing process from a single trusted entity to
various untrusted third-party entities worldwide. The risk of using untrusted
third-Party Intellectual Property (3PIP) is the possibility for adversaries to
insert malicious modifications known as Hardware Trojans (HTs). These HTs can
compromise the integrity, deteriorate the performance, deny the service, and
alter the functionality of the design. While numerous HT detection methods have
been proposed in the literature, the crucial task of HT localization is
overlooked. Moreover, a few existing HT localization methods have several
weaknesses: reliance on a golden reference, inability to generalize for all
types of HT, lack of scalability, low localization resolution, and manual
feature engineering/property definition. To overcome their shortcomings, we
propose a novel, golden reference-free HT localization method at the
pre-silicon stage by leveraging Graph Convolutional Network (GCN). In this
work, we convert the circuit design to its intrinsic data structure, graph and
extract the node attributes. Afterward, the graph convolution performs
automatic feature extraction for nodes to classify the nodes as Trojan or
benign. Our automated approach does not burden the designer with manual code
review. It locates the Trojan signals with 99.6% accuracy, 93.1% F1-score, and
a false-positive rate below 0.009%.

提出了一种基于 Graph Convolutional Network（GCN）的新型、无需 golden reference 的、预硅阶段硬件木马本地化方法，自动提取电路设计的节点特征进行分类，准确率达到 99.6％，F1 得分为 93.1％，假阳性率低于 0.009％。