High Performance Computing (HPC) benefits from different improvements during
last decades, specially in terms of hardware platforms to provide more
processing power while maintaining the power consumption at a reasonable level.
The Intelligence Processing Unit (IPU) is a new type of massively parallel
processor, designed to speedup parallel computations with huge number of
processing cores and on-chip memory components connected with high-speed
fabrics. IPUs mainly target machine learning applications, however, due to the
architectural differences between GPUs and IPUs, especially significantly less
memory capacity on an IPU, methods for reducing model size by sparsification
have to be considered. Butterfly factorizations are well-known replacements for
fully-connected and convolutional layers. In this paper, we examine how
butterfly structures can be implemented on an IPU and study their behavior and
performance compared to a GPU. Experimental results indicate that these methods
can provide 98.5% compression ratio to decrease the immense need for memory,
the IPU implementation can benefit from 1.3x and 1.6x performance improvement
for butterfly and pixelated butterfly, respectively. We also reach to 1.62x
training time speedup on a real-word dataset such as CIFAR10.

高性能计算从硬件平台的不断改进中受益，在保持合理功耗的同时提供更多的处理能力。智能处理单元（IPU）是一种新型的大规模并行处理器，旨在加速具有大量处理核心和高速内存组件的并行计算。本文研究了如何在 IPU 上实现蝶形结构，并研究了它们与 GPU 的行为和性能的比较。实验结果表明，这些方法可以提供 98.5% 的压缩比，减少对内存的极度需求。在蝶形和像素化蝶形方面，IPU 的实现可以获得 1.3 倍和 1.6 倍的性能改进。我们还在 CIFAR10 等实际数据集上实现了 1.62 倍的训练时间加速。

利用蝴蝶分解减少 IPU 的内存需求

Reducing Memory Requirements for the IPU using Butterfly Factorizations

This report focuses on the architecture and performance of the Intelligence
Processing Unit (IPU), a novel, massively parallel platform recently introduced
by Graphcore and aimed at Artificial Intelligence/Machine Learning (AI/ML)
workloads. We dissect the IPU's performance behavior using microbenchmarks that
we crafted for the purpose. We study the IPU's memory organization and
performance. We study the latency and bandwidth that the on-chip and off-chip
interconnects offer, both in point-to-point transfers and in a spectrum of
collective operations, under diverse loads. We evaluate the IPU's compute power
over matrix multiplication, convolution, and AI/ML primitives. We discuss
actual performance in comparison with its theoretical limits. Our findings
reveal how the IPU's architectural design affects its performance. Moreover,
they offer simple mental models to predict an application's performance on the
IPU, on the basis of the computation and communication steps it involves. This
report is the natural extension to a novel architecture of a continuing effort
of ours that focuses on the microbenchmark-based discovery of massively
parallel architectures.

本文介绍了新型、大规模并行平台 —— 智能处理单元（IPU）的架构和性能，并使用受其目的所驱动的微基准测试来剖析 IPU 的性能行为，同时研究了 IPU 的内存组织和性能、芯片内部和外部互连提供的延迟和带宽、计算能力以及与理论极限相比的实际性能表现，旨在为读者提供简单的心理模型，以便根据涉及的计算和通信步骤来预测应用程序在 IPU 上的性能。