Intrusion detection systems (IDS) are crucial security measures nowadays to
enforce network security. Their task is to detect anomalies in network
communication and identify, if not thwart, possibly malicious behavior.
Recently, machine learning has been deployed to construct intelligent IDS. This
approach, however, is quite challenging particularly in distributed, highly
dynamic, yet resource-constrained systems like Edge setups. In this paper, we
tackle this issue from multiple angles by analyzing the concept of intelligent
IDS (I-IDS) while addressing the specific requirements of Edge devices with a
special focus on reconfigurability. Then, we introduce a systematic approach to
constructing the I-IDS on reconfigurable Edge hardware. For this, we
implemented our proposed IDS on state-of-the-art Field Programmable Gate Arrays
(FPGAs) technology as (1) a purely FPGA-based dataflow processor (DFP) and (2)
a co-designed approach featuring RISC-V soft-core as FPGA-based soft-core
processor (SCP). We complete our paper with a comparison of the state of the
art (SoA) in this domain. The results show that DFP and SCP are both suitable
for Edge applications from hardware resource and energy efficiency
perspectives. Our proposed DFP solution clearly outperforms the SoA and
demonstrates that required high performance can be achieved without
prohibitively high hardware costs. This makes our proposed DFP suitable for
Edge-based high-speed applications like modern communication technology.

本文分析智能入侵检测系统（I-IDS）的概念，并针对边缘设备的特定需求以及可重构性等多个方面挑战，介绍了一种在可重构边缘硬件上构建智能入侵检测系统的系统化方法，通过实现所提出的纯 FPGA 数据流处理器（DFP）和以 RISC-V 软核为特色的基于 FPGA 的软核处理器（SCP）的共同设计方法，比较了该领域的现有技术。结果表明，DFP 和 SCP 在硬件资源和能量效率方面都适用于边缘应用，所提出的 DFP 解决方案明显优于现有技术，并且在不会引起过高硬件成本的情况下实现了所需的高性能，使其适用于现代通信技术等边缘高速应用。