Graph processors such as Graphcore's Intelligence Processing Unit (IPU) are
part of the major new wave of novel computer architecture for AI, and have a
general design with massively parallel computation, distributed on-chip memory
and very high inter-core communication bandwidth which allows breakthrough
performance for message passing algorithms on arbitrary graphs. We show for the
first time that the classical computer vision problem of bundle adjustment (BA)
can be solved extremely fast on a graph processor using Gaussian Belief
Propagation. Our simple but fully parallel implementation uses the 1216 cores
on a single IPU chip to, for instance, solve a real BA problem with 125
keyframes and 1919 points in under 40ms, compared to 1450ms for the Ceres CPU
library. Further code optimisation will surely increase this difference on
static problems, but we argue that the real promise of graph processing is for
flexible in-place optimisation of general, dynamically changing factor graphs
representing Spatial AI problems. We give indications of this with experiments
showing the ability of GBP to efficiently solve incremental SLAM problems, and
deal with robust cost functions and different types of factors.

本文研究了基于 Graphcore 智能处理单元（IPU）的图处理器，证明了用高斯置信传播算法可以极快地解决经典计算机视觉问题中的束调整问题，并表明图处理的真正优势在于处理表示空间 AI 问题的一般动态因子图的灵活本地优化。

基于图处理器的束调整

Bundle Adjustment on a Graph Processor

This report focuses on the architecture and performance of the Intelligence
Processing Unit (IPU), a novel, massively parallel platform recently introduced
by Graphcore and aimed at Artificial Intelligence/Machine Learning (AI/ML)
workloads. We dissect the IPU's performance behavior using microbenchmarks that
we crafted for the purpose. We study the IPU's memory organization and
performance. We study the latency and bandwidth that the on-chip and off-chip
interconnects offer, both in point-to-point transfers and in a spectrum of
collective operations, under diverse loads. We evaluate the IPU's compute power
over matrix multiplication, convolution, and AI/ML primitives. We discuss
actual performance in comparison with its theoretical limits. Our findings
reveal how the IPU's architectural design affects its performance. Moreover,
they offer simple mental models to predict an application's performance on the
IPU, on the basis of the computation and communication steps it involves. This
report is the natural extension to a novel architecture of a continuing effort
of ours that focuses on the microbenchmark-based discovery of massively
parallel architectures.

本文介绍了新型、大规模并行平台 —— 智能处理单元（IPU）的架构和性能，并使用受其目的所驱动的微基准测试来剖析 IPU 的性能行为，同时研究了 IPU 的内存组织和性能、芯片内部和外部互连提供的延迟和带宽、计算能力以及与理论极限相比的实际性能表现，旨在为读者提供简单的心理模型，以便根据涉及的计算和通信步骤来预测应用程序在 IPU 上的性能。