Temporal Convolutional Networks (TCNs) are emerging lightweight Deep Learning
models for Time Series analysis. We introduce an automated exploration approach
and a library of optimized kernels to map TCNs on Parallel Ultra-Low Power
(PULP) microcontrollers. Our approach minimizes latency and energy by
exploiting a layer tiling optimizer to jointly find the tiling dimensions and
select among alternative implementations of the causal and dilated
1D-convolution operations at the core of TCNs. We benchmark our approach on a
commercial PULP device, achieving up to 103X lower latency and 20.3X lower
energy than the Cube-AI toolkit executed on the STM32L4 and from 2.9X to 26.6X
lower energy compared to commercial closed-source and academic open-source
approaches on the same hardware target.

该论文介绍了一种基于自动探索方法和优化卷积核库的时间卷积网络应用于低功率微控制器上的策略，通过对层瓷砖的优化来达到最小延迟和能量消耗，实现了比其他常见方法更高效的时间序列分析方法。