Microarchitecture simulators are indispensable tools for microarchitecture
designers to validate, estimate, and optimize new hardware that meets specific
design requirements. While the quest for a fast, accurate and detailed
microarchitecture simulation has been ongoing for decades, existing simulators
excel and fall short at different aspects: (i) Although execution-driven
simulation is accurate and detailed, it is extremely slow and requires
expert-level experience to design. (ii) Trace-driven simulation reuses the
execution traces in pursuit of fast simulation but faces accuracy concerns and
fails to achieve significant speedup. (iii) Emerging deep learning (DL)-based
simulations are remarkably fast and have acceptable accuracy but fail to
provide adequate low-level microarchitectural performance metrics crucial for
microarchitectural bottleneck analysis. Additionally, they introduce
substantial overheads from trace regeneration and model re-training when
simulating a new microarchitecture.
Re-thinking the advantages and limitations of the aforementioned simulation
paradigms, this paper introduces TAO that redesigns the DL-based simulation
with three primary contributions: First, we propose a new training dataset
design such that the subsequent simulation only needs functional trace as
inputs, which can be rapidly generated and reused across microarchitectures.
Second, we redesign the input features and the DL model using self-attention to
support predicting various performance metrics. Third, we propose techniques to
train a microarchitecture agnostic embedding layer that enables fast transfer
learning between different microarchitectural configurations and reduces the
re-training overhead of conventional DL-based simulators. Our extensive
evaluation shows {\ours} can reduce the overall training and simulation time by
18.06x over the state-of-the-art DL-based endeavors.

本文介绍了 TAO，它通过重新设计基于深度学习的模拟方法，提出了一种新的训练数据集设计，使用自注意力机制重新设计输入特征和 DL 模型以预测各种性能指标，并提出了训练一个微架构不可知嵌入层的技术，可以在不同的微架构配置之间进行快速迁移学习，并减少传统 DL 模拟器的重新训练开销。经过广泛的评估，我们的方法相比于现有的 DL 模拟器能够减少总体的训练和模拟时间 18.06 倍。