Analog in-memory computing (AiMC) is an emerging technology that shows
fantastic performance superiority for neural network acceleration. However, as
the computational bit-width and scale increase, high-precision data conversion
and long-distance data routing will result in unacceptable energy and latency
overheads in the AiMC system. In this work, we focus on the potential of
in-charge computing and in-time interconnection and show an innovative AiMC
architecture, named AiDAC, with three key contributions: (1) AiDAC enhances
multibit computing efficiency and reduces data conversion times by grouping
capacitors technology; (2) AiDAC first adopts row drivers and column time
accumulators to achieve large-scale AiMC arrays integration while minimizing
the energy cost of data movements. (3) AiDAC is the first work to support
large-scale all-analog multibit vector-matrix multiplication (VMM) operations.
The evaluation shows that AiDAC maintains high-precision calculation (less than
0.79% total computing error) while also possessing excellent performance
features, such as high parallelism (up to 26.2TOPS), low latency (<20ns/VMM),
and high energy efficiency (123.8TOPS/W), for 8bits VMM with 1024 input
channels.

通过引入 In-charge computing 和 In-time interconnection 的创新 AiMC 架构 AiDAC，提高了多位计算效率，减少了数据转换时间，支持大规模的全模拟多位向量矩阵乘法运算，并保持高精度计算，同时具备高并行性、低延迟和高能效优势。