Generalized Sparse Matrix-Matrix Multiplication (SpGEMM) is a ubiquitous task
in various engineering and scientific applications. However, inner product
based SpGENN introduces redundant input fetches for mismatched nonzero
operands, while outer product based approach suffers from poor output locality
due to numerous partial product matrices. Inefficiency in the reuse of either
inputs or outputs data leads to extensive and expensive DRAM access.
To address this problem, this paper proposes an efficient sparse matrix
multiplication accelerator architecture, SpArch, which jointly optimizes the
data locality for both input and output matrices. We first design a highly
parallelized streaming-based merger to pipeline the multiply and merge stage of
partial matrices so that partial matrices are merged on chip immediately after
produced. We then propose a condensed matrix representation that reduces the
number of partial matrices by three orders of magnitude and thus reduces DRAM
access by 5.4x. We further develop a Huffman tree scheduler to improve the
scalability of the merger for larger sparse matrices, which reduces the DRAM
access by another 1.8x. We also resolve the increased input matrix read induced
by the new representation using a row prefetcher with near-optimal buffer
replacement policy, further reducing the DRAM access by 1.5x. Evaluated on 20
benchmarks, SpArch reduces the total DRAM access by 2.8x over previous
state-of-the-art. On average, SpArch achieves 4x, 19x, 18x, 17x, 1285x speedup
and 6x, 164x, 435x, 307x, 62x energy savings over OuterSPACE, MKL, cuSPARSE,
CUSP, and ARM Armadillo, respectively.

本文提出了一种有效的稀疏矩阵乘法加速架构 SpArch，它联合优化了输入和输出矩阵的数据局部性。通过设计高度并行化的基于流的合并器和一种压缩矩阵表示，该架构使总 DRAM 访问次数减少了 2.8x，平均速度提高了 4x - 1285x，节约了 6x-435x 能源。