This paper presents MicroNAS, a system designed to automatically search and
generate neural network architectures capable of classifying time series data
on resource-constrained microcontrollers (MCUs) and generating standard tf-lite
ML models. MicroNAS takes into account user-defined constraints on execution
latency and peak memory consumption on a target MCU. This approach ensures that
the resulting neural network architectures are optimised for the specific
constraints and requirements of the MCU on which they are implemented. To
achieve this, MicroNAS uses a look-up table estimation approach for accurate
execution latency calculations, with a minimum error of only 1.02ms. This
accurate latency estimation on MCUs sets it apart from other hardware-aware
neural architecture search (HW-NAS) methods that use less accurate estimation
techniques. Finally, MicroNAS delivers performance close to that of
state-of-the-art models running on desktop computers, achieving high
classification accuracies on recognised datasets (93.93% on UCI-HAR and 96.33%
on SkodaR) while running on a Cortex-M4 MCU.

MicroNAS 是一个系统，能够自动搜索和生成神经网络体系结构，用于分类时间序列数据，应用于资源受限的微控制器 (MCUs)，并生成标准 tf-lite ML 模型。