Photonic computing has emerged as a promising solution for accelerating
computation-intensive artificial intelligence (AI) workloads. However, limited
reconfigurability, high electrical-optical conversion cost, and thermal
sensitivity limit the deployment of current optical analog computing engines to
support power-restricted, performance-sensitive AI workloads at scale. Sparsity
provides a great opportunity for hardware-efficient AI accelerators. However,
current dense photonic accelerators fail to fully exploit the power-saving
potential of algorithmic sparsity. It requires sparsity-aware hardware
specialization with a fundamental re-design of photonic tensor core topology
and cross-layer device-circuit-architecture-algorithm co-optimization aware of
hardware non-ideality and power bottleneck. To trim down the redundant power
consumption while maximizing robustness to thermal variations, we propose
SCATTER, a novel algorithm-circuit co-sparse photonic accelerator featuring
dynamically reconfigurable signal path via thermal-tolerant, power-efficient
in-situ light redistribution and power gating. A power-optimized,
crosstalk-aware dynamic sparse training framework is introduced to explore
row-column structured sparsity and ensure marginal accuracy loss and maximum
power efficiency. The extensive evaluation shows that our cross-stacked
optimized accelerator SCATTER achieves a 511X area reduction and 12.4X power
saving with superior crosstalk tolerance that enables unprecedented circuit
layout compactness and on-chip power efficiency.

SCATTER 是一种算法电路共稀疏光子加速器，具有动态可重构信号路径、热容忍、功耗高效的特点，能够在最大程度上减少多余的功耗并保持对热变化的稳健性，达到 511 倍的面积减少和 12.4 倍的功率节约，具有卓越的串声容忍度，实现了前所未有的电路布局紧凑和芯片功耗效率。

SCATTER: 算法 - 电路协同稀疏光子加速器，具有热容忍、功耗高效的原位光重分布

SCATTER: Algorithm-Circuit Co-Sparse Photonic Accelerator with  Thermal-Tolerant, Power-Efficient In-situ Light Redistribution

Photonic computing shows promise for transformative advancements in machine
learning (ML) acceleration, offering ultra-fast speed, massive parallelism, and
high energy efficiency. However, current photonic tensor core (PTC) designs
based on standard optical components hinder scalability and compute density due
to their large spatial footprint. To address this, we propose an ultra-compact
PTC using customized programmable multi-operand multimode interference (MOMMI)
devices, named M3ICRO. The programmable MOMMI leverages the intrinsic light
propagation principle, providing a single-device programmable matrix unit
beyond the conventional computing paradigm of one multiply-accumulate (MAC)
operation per device. To overcome the optimization difficulty of customized
devices that often requires time-consuming simulation, we apply ML for optics
to predict the device behavior and enable a differentiable optimization flow.
We thoroughly investigate the reconfigurability and matrix expressivity of our
customized PTC, and introduce a novel block unfolding method to fully exploit
the computing capabilities of a complex-valued PTC for near-universal
real-valued linear transformations. Extensive evaluations demonstrate that
M3ICRO achieves a 3.4-9.6x smaller footprint, 1.6-4.4x higher speed, 10.6-42x
higher compute density, 3.7-12x higher system throughput, and superior noise
robustness compared to state-of-the-art coherent PTC designs, while maintaining
close-to-digital task accuracy across various ML benchmarks. Our code is
open-sourced at this https URL

提出了一种名为 M3ICRO 的基于多路多模干涉（MOMMI）器件定制的可编程光子张量芯片，在充分利用光电计算的能力的同时具有高能效、小体积以及优异的噪声鲁棒性。