FPGAs have distinct advantages as a technology for deploying deep neural
networks (DNNs) at the edge. Lookup Table (LUT) based networks, where neurons
are directly modelled using LUTs, help maximize this promise of offering
ultra-low latency and high area efficiency on FPGAs. Unfortunately, LUT
resource usage scales exponentially with the number of inputs to the LUT,
restricting PolyLUT to small LUT sizes. This work introduces PolyLUT-Add, a
technique that enhances neuron connectivity by combining $A$ PolyLUT
sub-neurons via addition to improve accuracy. Moreover, we describe a novel
architecture to improve its scalability. We evaluated our implementation over
the MNIST, Jet Substructure classification and Network Intrusion Detection
benchmark and found that for similar accuracy, PolyLUT-Add achieves a LUT
reduction of $1.3-7.7\times$ with a $1.2-2.2\times$ decrease in latency.

通过引入 PolyLUT-Add 技术，结合多个 PolyLUT 子神经元进行相加以提高准确性，并描述了一个提高可扩展性的新型架构，实验结果表明，在相似准确度的情况下，PolyLUT-Add 相比传统方法能够减少 1.3-7.7 倍的 LUT 使用量并降低 1.2-2.2 倍的延迟。