This paper presents a mixed-computation neural network processing approach
for edge applications that incorporates low-precision (low-width) Posit and
low-precision fixed point (FixP) number systems. This mixed-computation
approach employs 4-bit Posit (Posit4), which has higher precision around zero,
for representing weights with high sensitivity, while it uses 4-bit FixP
(FixP4) for representing other weights. A heuristic for analyzing the
importance and the quantization error of the weights is presented to assign the
proper number system to different weights. Additionally, a gradient
approximation for Posit representation is introduced to improve the quality of
weight updates in the backpropagation process. Due to the high energy
consumption of the fully Posit-based computations, neural network operations
are carried out in FixP or Posit/FixP. An efficient hardware implementation of
a MAC operation with a first Posit operand and FixP for a second operand and
accumulator is presented. The efficacy of the proposed low-precision
mixed-computation approach is extensively assessed on vision and language
models. The results show that, on average, the accuracy of the
mixed-computation is about 1.5% higher than that of FixP with a cost of 0.19%
energy overhead.

该研究论文提出了一种混合计算神经网络处理方法，通过低精度的 Posit 和低精度定点 FixP 数值系统，为边缘应用提供支持，并利用启发式方法分析权重的重要性和量化误差，为不同权重分配正确的数值系统。通过在视觉和语言模型上的广泛评估，结果显示混合计算的准确性平均比 FixP 高约 1.5%，只需 0.19% 的能量开销。

边缘推断的低精度混合计算模型

Low-Precision Mixed-Computation Models for Inference on Edge

As recently demonstrated, Deep Neural Networks (DNN), usually trained using
single precision IEEE 754 floating point numbers (binary32), can also work
using lower precision. Therefore, 16-bit and 8-bit compressed format have
attracted considerable attention. In this paper, we focused on two families of
formats that have already achieved interesting results in compressing binary32
numbers in machine learning applications, without sensible degradation of the
accuracy: bfloat and posit. Even if 16-bit and 8-bit bfloat/posit are routinely
used for reducing the storage of the weights/biases of trained DNNs, the
inference still often happens on the 32-bit FPU of the CPU (especially if GPUs
are not available). In this paper we propose a way to decompress a tensor of
bfloat/posits just before computations, i.e., after the compressed operands
have been loaded within the vector registers of a vector capable CPU, in order
to save bandwidth usage and increase cache efficiency. Finally, we show the
architectural parameters and considerations under which this solution is
advantageous with respect to the uncompressed one.

本文提出了一种在计算之前解压缩 bfloat/posit 张量的方法，以节省带宽使用并增加缓存效率，同时展示了与未压缩数据相比，在架构参数和考虑因素下该解决方案的优势。

用于人工智能的压缩实数：以 RISC-V CPU 为案例研究

Compressed Real Numbers for AI: a case-study using a RISC-V CPU

Posit has been a promising alternative to the IEEE-754 floating point format
for deep learning applications due to its better trade-off between dynamic
range and accuracy. However, hardware implementation of posit arithmetic
requires further exploration, especially for the dot-product operations
dominated in deep neural networks (DNNs). It has been implemented by either the
combination of multipliers and an adder tree or cascaded fused multiply-add
units, leading to poor computational efficiency and excessive hardware
overhead. To address this issue, we propose an open-source posit dot-product
unit, namely PDPU, that facilitates resource-efficient and high-throughput
dot-product hardware implementation. PDPU not only features the fused and
mixed-precision architecture that eliminates redundant latency and hardware
resources, but also has a fine-grained 6-stage pipeline, improving
computational efficiency. A configurable PDPU generator is further developed to
meet the diverse needs of various DNNs for computational accuracy. Experimental
results evaluated under the 28nm CMOS process show that PDPU reduces area,
latency, and power by up to 43%, 64%, and 70%, respectively, compared to the
existing implementations. Hence, PDPU has great potential as the computing core
of posit-based accelerators for deep learning applications.

该研究提出了一个名为 PDPU 的开源端点积处理器单元，旨在促进资源高效和高吞吐量的端点积硬件实现，通过优化后的硬件架构和流水线设计，可以显著降低面积、延迟和功耗，具有成为基于端点积加速器的计算核心的巨大潜力。