Low-precision DNNs have been extensively explored in order to reduce the size
of DNN models for edge devices. Recently, the posit numerical format has shown
promise for DNN data representation and compute with ultra-low precision in
[5..8]-bits. However, previous studies were limited to studying posit for DNN
inference only. In this paper, we propose the Cheetah framework, which supports
both DNN training and inference using posits, as well as other commonly used
formats. Additionally, the framework is amenable for different quantization
approaches and supports mixed-precision floating point and fixed-point
numerical formats. Cheetah is evaluated on three datasets: MNIST, Fashion
MNIST, and CIFAR-10. Results indicate that 16-bit posits outperform 16-bit
floating point in DNN training. Furthermore, performing inference with
[5..8]-bit posits improves the trade-off between performance and
energy-delay-product over both [5..8]-bit float and fixed-point.

本文提出了 Cheetah 框架，支持使用超低精度的 posits 格式进行 DNN 训练和推理，同时支持混合精度和其他常用的数值格式，并在 MNIST、Fashion MNIST 和 CIFAR-10 三个数据集上进行了评估。结果表明，用 16 位 posits 进行 DNN 训练可以优于使用 16 位浮点数，并且使用 [5..8] 位 posits 进行推理可以改善性能和能耗之间的折衷。

Cheetah：边缘 DNN 的混合低精度硬件和软件协同设计框架

Cheetah: Mixed Low-Precision Hardware & Software Co-Design Framework for  DNNs on the Edge

The recent surge of interest in Deep Neural Networks (DNNs) has led to
increasingly complex networks that tax computational and memory resources. Many
DNNs presently use 16-bit or 32-bit floating point operations. Significant
performance and power gains can be obtained when DNN accelerators support
low-precision numerical formats. Despite considerable research, there is still
a knowledge gap on how low-precision operations can be realized for both DNN
training and inference. In this work, we propose a DNN architecture, Deep
Positron, with posit numerical format operating successfully at $\leq$8 bits
for inference. We propose a precision-adaptable FPGA soft core for exact
multiply-and-accumulate for uniform comparison across three numerical formats,
fixed, floating-point and posit. Preliminary results demonstrate that 8-bit
posit has better accuracy than 8-bit fixed or floating-point for three
different low-dimensional datasets. Moreover, the accuracy is comparable to
32-bit floating-point on a Xilinx Virtex-7 FPGA device. The trade-offs between
DNN performance and hardware resources, i.e. latency, power, and resource
utilization, show that posit outperforms in accuracy and latency at 8-bit and
below.

该论文提出一种基于 posit 数值格式的 DNN 体系结构及可调精度 FPGA 软核，通过实验结果表明，该体系结构在 8 位或以下的 posit 数值格式下，性能和精度均优于传统的固定位数和浮点数位数格式，提示该方法能够在减小计算资源的同时提高 DNN 的性能。