High-level synthesis (HLS) notably speeds up the hardware design process by
avoiding RTL programming. However, the turnaround time of HLS increases
significantly when post-route quality of results (QoR) are considered during
optimization. To tackle this issue, we propose a hierarchical post-route QoR
prediction approach for FPGA HLS, which features: (1) a modeling flow that
directly estimates latency and post-route resource usage from C/C++ programs;
(2) a graph construction method that effectively represents the control and
data flow graph of source code and effects of HLS pragmas; and (3) a
hierarchical GNN training and prediction method capable of capturing the impact
of loop hierarchies. Experimental results show that our method presents a
prediction error of less than 10% for different types of QoR metrics, which
gains tremendous improvement compared with the state-of-the-art GNN methods. By
adopting our proposed methodology, the runtime for design space exploration in
HLS is shortened to tens of minutes and the achieved ADRS is reduced to 6.91%
on average.

高层次综合通过避免 RTL 编程显著加速了硬件设计过程。然而，当考虑了后布线结果质量（QoR）时，高层次综合的周转时间显著增加。为了解决这个问题，我们提出了一种用于 FPGA 高层次综合的分层后布线 QoR 预测方法，它具有：（1）一种从 C/C++ 程序直接估计延迟和后布线资源使用的建模流程；（2）一种有效表示源代码的控制流图和数据流图以及高层次综合指令的影响的图构建方法；（3）一种能够捕捉循环层次影响的分层 GNN 训练和预测方法。实验结果表明，我们的方法对于不同类型的 QoR 指标的预测误差小于 10%，相比于最先进的 GNN 方法有了巨大的改进。通过采用我们提出的方法，高层次综合中的设计空间探索运行时间缩短到了几十分钟，平均实现的 ADRS 值降低到了 6.91%。