The paper focuses on real-time facial expression recognition (FER) systems as
an important component in various real-world applications such as social
robotics. We investigate two hardware options for the deployment of FER machine
learning (ML) models at the edge: neuromorphic hardware versus edge AI
accelerators. Our study includes exhaustive experiments providing comparative
analyses between the Intel Loihi neuromorphic processor and four distinct edge
platforms: Raspberry Pi-4, Intel Neural Compute Stick (NSC), Jetson Nano, and
Coral TPU. The results obtained show that Loihi can achieve approximately two
orders of magnitude reduction in power dissipation and one order of magnitude
energy savings compared to Coral TPU which happens to be the least
power-intensive and energy-consuming edge AI accelerator. These reductions in
power and energy are achieved while the neuromorphic solution maintains a
comparable level of accuracy with the edge accelerators, all within the
real-time latency requirements.

本研究聚焦于实时人脸表情识别（FER）系统作为社会机器人等各种现实世界应用的重要组成部分。我们调查了两种用于边缘部署 FER 机器学习（ML）模型的硬件选择：神经形态硬件和边缘 AI 加速器。我们的研究包括详尽的实验，对比分析了 Intel Loihi 神经形态处理器与四种不同的边缘平台：Raspberry Pi-4、Intel Neural Compute Stick（NSC）、Jetson Nano 和 Coral TPU。实验结果表明，Loihi 与边缘加速器相比，能够实现功耗降低约两个数量级，以及能耗节约约一个数量级。这些功耗和能耗的降低是在维持神经形态解决方案与边缘加速器相当准确性的情况下实现的，而且都在实时延迟要求内。

实时面部表情识别：神经形态硬件对边缘人工智能加速器的比较

Realtime Facial Expression Recognition: Neuromorphic Hardware vs. Edge  AI Accelerators

We propose a Digit-Serial Left-tO-righT (DSLOT) arithmetic based processing
technique called DSLOT-NN with aim to accelerate inference of the convolution
operation in the deep neural networks (DNNs). The proposed work has the ability
to assess and terminate the ineffective convolutions which results in massive
power and energy savings. The processing engine is comprised of low-latency
most-significant-digit-first (MSDF) (also called online) multipliers and adders
that processes data from left-to-right, allowing the execution of subsequent
operations in digit-pipelined manner. Use of online operators eliminates the
need for the development of complex mechanism of identifying the negative
activation, as the output with highest weight value is generated first, and the
sign of the result can be identified as soon as first non-zero digit is
generated. The precision of the online operators can be tuned at run-time,
making them extremely useful in situations where accuracy can be compromised
for power and energy savings. The proposed design has been implemented on
Xilinx Virtex-7 FPGA and is compared with state-of-the-art Stripes on various
performance metrics. The results show the proposed design presents power
savings, has shorter cycle time, and approximately 50% higher OPS per watt.

我们提出了一种基于 DSLOT-NN 的 Digit-Serial Left-tO-righT（DSLOT）算术处理技术，旨在加速深度神经网络（DNNs）中卷积操作的推断。该提出的方法能够评估和停止无效的卷积操作，从而实现大规模的功率和能量节省。