To effectively implement quantum algorithms on noisy intermediate-scale
quantum (NISQ) processors is a central task in modern quantum technology. NISQ
processors feature tens to a few hundreds of noisy qubits with limited
coherence times and gate operations with errors, so NISQ algorithms naturally
require employing circuits of short lengths via quantum compilation. Here, we
develop a reinforcement learning (RL)-based quantum compiler for a
superconducting processor and demonstrate its capability of discovering novel
and hardware-amenable circuits with short lengths. We show that for the
three-qubit quantum Fourier transformation, a compiled circuit using only seven
CZ gates with unity circuit fidelity can be achieved. The compiler is also able
to find optimal circuits under device topological constraints, with lengths
considerably shorter than those by the conventional method. Our study
exemplifies the codesign of the software with hardware for efficient quantum
compilation, offering valuable insights for the advancement of RL-based
compilers.

我们开发了一个基于强化学习的量子编译器，对超导处理器进行了演示，展示了其发现具有短长度的新型硬件友好电路的能力，并能够在设备拓扑约束下找到最佳电路。