The proliferation of edge devices necessitates efficient computational
architectures for lightweight tasks, particularly deep neural network (DNN)
inference. Traditional NPUs, though effective for such operations, face
challenges in power, cost, and area when integrated into lightweight edge
devices. The RISC-V architecture, known for its modularity and open-source
nature, offers a viable alternative. This paper introduces the RISC-V
R-extension, a novel approach to enhancing DNN process efficiency on edge
devices. The extension features rented-pipeline stages and architectural
pipeline registers (APR), which optimize critical operation execution, thereby
reducing latency and memory access frequency. Furthermore, this extension
includes new custom instructions to support these architectural improvements.
Through comprehensive analysis, this study demonstrates the boost of
R-extension in edge device processing, setting the stage for more responsive
and intelligent edge applications.

该研究介绍了 RISC-V R-extension，一种用于增强边缘设备上深度神经网络处理效率的新方法。该扩展采用了租用流水线阶段和架构流水线寄存器（APR）的特性，优化关键操作执行，从而减少延迟和内存访问频率，通过全面分析，证明了 R-extension 在边缘设备处理中的提升效果，为更加响应和智能的边缘应用铺平了道路。