Power side-channel (PSC) analysis is pivotal for securing cryptographic
hardware. Prior art focused on securing gate-level netlists obtained as-is from
chip design automation, neglecting all the complexities and potential
side-effects for security arising from the design automation process. That is,
automation traditionally prioritizes power, performance, and area (PPA),
sidelining security. We propose a "security-first" approach, refining the logic
synthesis stage to enhance the overall resilience of PSC countermeasures. We
introduce ASCENT, a learning-and-search-based framework that (i) drastically
reduces the time for post-design PSC evaluation and (ii) explores the
security-vs-PPA design space. Thus, ASCENT enables an efficient exploration of
a large number of candidate netlists, leading to an improvement in PSC
resilience compared to regular PPA-optimized netlists. ASCENT is up to 120x
faster than traditional PSC analysis and yields a 3.11x improvement for PSC
resilience of state-of-the-art PSC countermeasures

通过引入一种基于学习和搜索的框架 ASCENT，本研究提出了一种以安全为主导的方法来改进逻辑综合阶段，从而提高功耗侧信道抵抗措施的整体弹性，该方法能够显著减少后期设计中功耗侧信道评估的时间，并探索安全性与功耗性能之间的设计空间，相较于传统的功耗性能优化网表，ASCENT 在功耗侧信道抵抗措施方面表现出了相当大的提升。