In recent years, analog circuits have received extensive attention and are
widely used in many emerging applications. The high demand for analog circuits
necessitates shorter circuit design cycles. To achieve the desired performance
and specifications, various geometrical symmetry constraints must be carefully
considered during the analog layout process. However, the manual labeling of
these constraints by experienced analog engineers is a laborious and
time-consuming process. To handle the costly runtime issue, we propose a
graph-based learning framework to automatically extract symmetric constraints
in analog circuit layout. The proposed framework leverages the connection
characteristics of circuits and the devices'information to learn the general
rules of symmetric constraints, which effectively facilitates the extraction of
device-level constraints on circuit netlists. The experimental results
demonstrate that compared to state-of-the-art symmetric constraint detection
approaches, our framework achieves higher accuracy and lower false positive
rate.

提出了一种基于图的学习框架，用于自动提取模拟电路布局中的对称约束，并通过实验证明相比现有的对称约束检测方法，该框架在准确性和错误率方面具有更高的性能。