Modern System-on-Chip (SoC) designs are becoming more and more complex due to
the technology upscaling. SoC designs often operate on multiple asynchronous
clock domains, further adding to the complexity of the overall design. To make
the devices power efficient, designers take a Globally-Asynchronous
Locally-Synchronous (GALS) approach that creates multiple asynchronous domains.
These Clock Domain Crossings (CDC) are prone to metastability effects, and
functional verification of such CDC is very important to ensure that no bug
escapes. Conventional verification methods, such as register transfer level
(RTL) simulations and static timing analysis, are not enough to address these
CDC issues, which may lead to verification gaps. Additionally, identifying
these CDC-related bugs is very time-consuming and is one of the most common
reasons for costly silicon re-spins. This paper is focused on the development
of a pragmatic formal verification methodology to minimize the CDC issues by
exercising Metastability Injection (MSI) in different CDC paths.

本文针对现代芯片设计中的多个异步时钟域和时钟域交叉问题，提出了一种形式化验证方法，通过在不同的时钟域路径中注入不稳定性来减少时钟域交叉问题。

钟域交叉的实用形式验证方法

Pragmatic Formal Verification Methodology for Clock Domain Crossing  (CDC)

As the ubiquity and complexity of system-on-chip (SoC) designs increase
across electronic devices, the task of incorporating security into an SoC
design flow poses significant challenges. Existing security solutions are
inadequate to provide effective verification of modern SoC designs due to their
limitations in scalability, comprehensiveness, and adaptability. On the other
hand, Large Language Models (LLMs) are celebrated for their remarkable success
in natural language understanding, advanced reasoning, and program synthesis
tasks. Recognizing an opportunity, our research delves into leveraging the
emergent capabilities of Generative Pre-trained Transformers (GPTs) to address
the existing gaps in SoC security, aiming for a more efficient, scalable, and
adaptable methodology. By integrating LLMs into the SoC security verification
paradigm, we open a new frontier of possibilities and challenges to ensure the
security of increasingly complex SoCs. This paper offers an in-depth analysis
of existing works, showcases practical case studies, demonstrates comprehensive
experiments, and provides useful promoting guidelines. We also present the
achievements, prospects, and challenges of employing LLM in different SoC
security verification tasks.

通过整合大型语言模型（LLMs）到 SoC 安全验证范式中，我们在现有 SoC 安全方案的限制性能、全面性和适应性方面的差距中开辟了新的可能性和挑战，旨在实现更高效、可扩展和可适应的方法。

LLM 用于 SoC 安全：范式转变

LLM for SoC Security: A Paradigm Shift

High-quality system-level message flow specifications are necessary for
comprehensive validation of system-on-chip (SoC) designs. However, manual
development and maintenance of such specifications are daunting tasks. We
propose a disruptive method that utilizes deep sequence modeling with the
attention mechanism to infer accurate flow specifications from SoC
communication traces. The proposed method can overcome the inherent complexity
of SoC traces induced by the concurrent executions of SoC designs that existing
mining tools often find extremely challenging. We conduct experiments on five
highly concurrent traces and find that the proposed approach outperforms
several existing state-of-the-art trace mining tools.

利用深层序列建模和注意机制，从 SoC 通信跟踪数据中推断准确的流规范，以克服现有挖掘工具 often often 面临的复杂性挑战，实验证明该方法胜过多种现有工具。

使用注意力模型挖掘 SoC 消息流

Mining SoC Message Flows with Attention Model

Neural schedulers based on deep reinforcement learning (DRL) have shown
considerable potential for solving real-world resource allocation problems, as
they have demonstrated significant performance gain in the domain of cluster
computing. In this paper, we investigate the feasibility of neural schedulers
for the domain of System-on-Chip (SoC) resource allocation through extensive
experiments and comparison with non-neural, heuristic schedulers. The key
finding is three-fold. First, neural schedulers designed for cluster computing
domain do not work well for SoC due to i) heterogeneity of SoC computing
resources and ii) variable action set caused by randomness in incoming jobs.
Second, our novel neural scheduler technique, Eclectic Interaction Matching
(EIM), overcomes the above challenges, thus significantly improving the
existing neural schedulers. Specifically, we rationalize the underlying reasons
behind the performance gain by the EIM-based neural scheduler. Third, we
discover that the ratio of the average processing elements (PE) switching delay
and the average PE computation time significantly impacts the performance of
neural SoC schedulers even with EIM. Consequently, future neural SoC scheduler
design must consider this metric as well as its implementation overhead for
practical utility.

通过与非神经、启发式任务调度器的比较，本文通过广泛实验研究和深度强化学习探究了基于 DRL 的神经调度器在 SoC 资源分配领域的实现可能性，并提出了 Eclectic Interaction Matching 技术以改进现有的神经调度器