Machine learning (ML) is successful in achieving human-level artificial
intelligence in various fields. However, it lacks the ability to explain an
outcome due to its black-box nature. While recent efforts on explainable AI
(XAI) has received significant attention, most of the existing solutions are
not applicable in real-time systems since they map interpretability as an
optimization problem, which leads to numerous iterations of time-consuming
complex computations. Although there are existing hardware-based acceleration
framework for XAI, they are implemented through FPGA and designed for specific
tasks, leading to expensive cost and lack of flexibility. In this paper, we
propose a simple yet efficient framework to accelerate various XAI algorithms
with existing hardware accelerators. Specifically, this paper makes three
important contributions. (1) The proposed method is the first attempt in
exploring the effectiveness of Tensor Processing Unit (TPU) to accelerate XAI.
(2) Our proposed solution explores the close relationship between several
existing XAI algorithms with matrix computations, and exploits the synergy
between convolution and Fourier transform, which takes full advantage of TPU's
inherent ability in accelerating matrix computations. (3) Our proposed approach
can lead to real-time outcome interpretation. Extensive experimental evaluation
demonstrates that proposed approach deployed on TPU can provide drastic
improvement in interpretation time (39x on average) as well as energy
efficiency (69x on average) compared to existing acceleration techniques.

本研究提出一种简单且高效的框架，通过存在的硬件加速器来加速各种 XAI 算法，并探索了 Tensor Processing Unit（TPU）加速 XAI 的有效性，利用卷积和傅里叶变换之间的协同关系，充分利用 TPU 在加速矩阵计算方面的本能能力，这种方法可以带来实时结果解释。与现有加速技术相比，基于 TPU 的提议方法可以提供对结果解释时间的巨大改善（平均 39 倍）以及能源效率（平均 69 倍）方面的提升。

可解释人工智能的硬件加速

Hardware Acceleration of Explainable Artificial Intelligence

Multi-level intermediate representations (MLIR) show great promise for
reducing the cost of building domain-specific compilers by providing a reusable
and extensible compiler infrastructure. This work presents TPU-MLIR, an
end-to-end compiler based on MLIR that deploys pre-trained neural network (NN)
models to a custom ASIC called a Tensor Processing Unit (TPU). TPU-MLIR defines
two new dialects to implement its functionality: 1. a Tensor operation (TOP)
dialect that encodes the deep learning graph semantics and independent of the
deep learning framework and 2. a TPU kernel dialect to provide a standard
kernel computation on TPU. A NN model is translated to the TOP dialect and then
lowered to the TPU dialect for different TPUs according to the chip's
configuration. We demonstrate how to use the MLIR pass pipeline to organize and
perform optimization on TPU to generate machine code. The paper also presents a
verification procedure to ensure the correctness of each transform stage.

本篇研究利用多层中间表示（MLIR）提供可重用和可扩展的编译器基础，并提出 TPU-MLIR，通过两个新的方言（Tensor 操作和 TPU 内核）将神经网络模型部署到自定义 ASIC，使用 MLIR 传递管道在 TPU 上进行优化以生成机器代码。

TPU-MLIR：使用 MLIR 的 TPU 编译器

TPU-MLIR: A Compiler For TPU Using MLIR

Many architects believe that major improvements in cost-energy-performance
must now come from domain-specific hardware. This paper evaluates a custom
ASIC---called a Tensor Processing Unit (TPU)---deployed in datacenters since
2015 that accelerates the inference phase of neural networks (NN). The heart of
the TPU is a 65,536 8-bit MAC matrix multiply unit that offers a peak
throughput of 92 TeraOps/second (TOPS) and a large (28 MiB) software-managed
on-chip memory. The TPU's deterministic execution model is a better match to
the 99th-percentile response-time requirement of our NN applications than are
the time-varying optimizations of CPUs and GPUs (caches, out-of-order
execution, multithreading, multiprocessing, prefetching, ...) that help average
throughput more than guaranteed latency. The lack of such features helps
explain why, despite having myriad MACs and a big memory, the TPU is relatively
small and low power. We compare the TPU to a server-class Intel Haswell CPU and
an Nvidia K80 GPU, which are contemporaries deployed in the same datacenters.
Our workload, written in the high-level TensorFlow framework, uses production
NN applications (MLPs, CNNs, and LSTMs) that represent 95% of our datacenters'
NN inference demand. Despite low utilization for some applications, the TPU is
on average about 15X - 30X faster than its contemporary GPU or CPU, with
TOPS/Watt about 30X - 80X higher. Moreover, using the GPU's GDDR5 memory in the
TPU would triple achieved TOPS and raise TOPS/Watt to nearly 70X the GPU and
200X the CPU.

本研究是对 Tensor Processing Unit (TPU) 这种加速神经网络 (NN) 推理阶段的定制 ASIC 进行的评估，与同样部署在数据中心的 Intel Haswell CPU 和 Nvidia K80 GPU 相比，TPU 在保证相应时间的情况下比 GPU 或 CPU 平均快 15 倍 - 30 倍，TOPS/Watt 比 GPU 提高近 70 倍，比 CPU 提高 200 倍。