The application of Machine Learning (ML) in Electronic Design Automation
(EDA) for Very Large-Scale Integration (VLSI) design has garnered significant
research attention. Despite the requirement for extensive datasets to build
effective ML models, most studies are limited to smaller, internally generated
datasets due to the lack of comprehensive public resources. In response, we
introduce EDALearn, the first holistic, open-source benchmark suite
specifically for ML tasks in EDA. This benchmark suite presents an end-to-end
flow from synthesis to physical implementation, enriching data collection
across various stages. It fosters reproducibility and promotes research into ML
transferability across different technology nodes. Accommodating a wide range
of VLSI design instances and sizes, our benchmark aptly represents the
complexity of contemporary VLSI designs. Additionally, we provide an in-depth
data analysis, enabling users to fully comprehend the attributes and
distribution of our data, which is essential for creating efficient ML models.
Our contributions aim to encourage further advances in the ML-EDA domain.

机器学习在电子设计自动化（EDA）和大规模集成电路（VLSI）设计中的应用引起了大量研究关注，本研究介绍了 EDALearn，一个综合的开源基准套件，特别用于 EDA 中的机器学习任务，以促进不同技术节点之间的机器学习可迁移性研究，并提供详细的数据分析，以帮助用户充分理解数据属性和分布。

EDALearn: 面向 EDA 研究的全面 RTL 到最终工艺工具（Signoff EDA）的性能基准测试

EDALearn: A Comprehensive RTL-to-Signoff EDA Benchmark for Democratized  and Reproducible ML for EDA Research

The development of very large-scale integration (VLSI) technology has posed
new challenges for electronic design automation (EDA) techniques in chip
floorplanning. During this process, macro placement is an important subproblem,
which tries to determine the positions of all macros with the aim of minimizing
half-perimeter wirelength (HPWL) and avoiding overlapping. Previous methods
include packing-based, analytical and reinforcement learning methods. In this
paper, we propose a new black-box optimization (BBO) framework (called
WireMask-BBO) for macro placement, by using a wire-mask-guided greedy procedure
for objective evaluation. Equipped with different BBO algorithms, WireMask-BBO
empirically achieves significant improvements over previous methods, i.e.,
achieves significantly shorter HPWL by using much less time. Furthermore, it
can fine-tune existing placements by treating them as initial solutions, which
can bring up to 50% improvement in HPWL. WireMask-BBO has the potential to
significantly improve the quality and efficiency of chip floorplanning, which
makes it appealing to researchers and practitioners in EDA and will also
promote the application of BBO.

本研究提出了一种基于黑箱优化（BBO）框架（称为 WireMask-BBO）的宏单元布局方法，通过使用电线掩蔽引导的贪婪过程进行目标评估。该算法在缩短半长度周边线的同时，大大节约了时间，具有在芯片布局方面提高质量和效率的潜力。