Heterogeneous computing is emerging as a mandatory requirement for
power-efficient system design. With this aim, modern heterogeneous platforms
like Zynq All-Programmable SoC, that integrates ARM-based SMP and programmable
logic, have been designed. However, those platforms introduce large design
cycles consisting on hardware/software partitioning, decisions on granularity
and number of hardware accelerators, hardware/software integration, bitstream
generation, etc.
This paper presents a performance parallel heterogeneous estimation for
systems where hardware/software co-design and run-time heterogeneous task
scheduling are key. The results show that the programmer can quickly decide,
based only on her/his OmpSs (OpenMP + extensions) application, which is the
co-design that achieves nearly optimal heterogeneous parallel performance,
based on the methodology presented and considering only synthesis estimation
results. The methodology presented reduces the programmer co-design decision
from hours to minutes and shows high potential on hardware/software
heterogeneous parallel performance estimation on the Zynq All-Programmable SoC.

本文介绍了用于系统性能并行异构估计的一种新方法，并对 Zynq All-Programmable SoC 上的硬件 / 软件异构并行表现进行了评估。