Nonlinear behavior in the hopping transport of interacting charges enables
reconfigurable logic in disordered dopant network devices, where voltages
applied at control electrodes tune the relation between voltages applied at
input electrodes and the current measured at an output electrode. From kinetic
Monte Carlo simulations we analyze the critical nonlinear aspects of
variable-range hopping transport for realizing Boolean logic gates in these
devices on three levels. First, we quantify the occurrence of individual gates
for random choices of control voltages. We find that linearly inseparable gates
such as the XOR gate are less likely to occur than linearly separable gates
such as the AND gate, despite the fact that the number of different regions in
the multidimensional control voltage space for which AND or XOR gates occur is
comparable. Second, we use principal component analysis to characterize the
distribution of the output current vectors for the (00,10,01,11) logic input
combinations in terms of eigenvectors and eigenvalues of the output covariance
matrix. This allows a simple and direct comparison of the behavior of different
simulated devices and a comparison to experimental devices. Third, we quantify
the nonlinearity in the distribution of the output current vectors necessary
for realizing Boolean functionality by introducing three nonlinearity
indicators. The analysis provides a physical interpretation of the effects of
changing the hopping distance and temperature and is used in a comparison with
data generated by a deep neural network trained on a physical device.

非线性行为对于在无序杂质网络器件中的跳跃输运具有重要作用，通过控制电极施加的电压可以调整输入电极施加的电压与输出电极测量的电流之间的关系，在此基础上使用 Monte Carlo 模拟分析可变范围跳跃输运的关键非线性方面，以实现布尔逻辑门。

无序掺杂网络中可重构逻辑的关键非线性跳跃传输方面

Critical nonlinear aspects of hopping transport for reconfigurable logic  in disordered dopant networks

Logic synthesis is the first and most vital step in chip design. This steps
converts a chip specification written in a hardware description language (such
as Verilog) into an optimized implementation using Boolean logic gates.
State-of-the-art logic synthesis algorithms have a large number of logic
minimization heuristics, typically applied sequentially based on human
experience and intuition. The choice of the order greatly impacts the quality
(e.g., area and delay) of the synthesized circuit. In this paper, we propose
INVICTUS, a model-based offline reinforcement learning (RL) solution that
automatically generates a sequence of logic minimization heuristics ("synthesis
recipe") based on a training dataset of previously seen designs. A key
challenge is that new designs can range from being very similar to past designs
(e.g., adders and multipliers) to being completely novel (e.g., new processor
instructions). %Compared to prior work, INVICTUS is the first solution that
uses a mix of RL and search methods joint with an online out-of-distribution
detector to generate synthesis recipes over a wide range of benchmarks. Our
results demonstrate significant improvement in area-delay product (ADP) of
synthesized circuits with up to 30\% improvement over state-of-the-art
techniques. Moreover, INVICTUS achieves up to $6.3\times$ runtime reduction
(iso-ADP) compared to the state-of-the-art.

研究提出了 INVICTUS，一个基于模型的离线强化学习（RL）解决方案，可自动生成一系列基于先前设计的训练数据集的逻辑化简启发式的序列，以用于芯片设计的逻辑合成。结果表明，与最先进的技术相比，INVICTUS 在合成电路的面积时延乘积（ADP）方面有显着改进，改进达到了最先进技术的 30% ，同时在运行时间方面还实现了高达 6.3 倍的降低。