Emerging AI applications such as ChatGPT, graph convolutional networks, and
other deep neural networks require massive computational resources for training
and inference. Contemporary computing platforms such as CPUs, GPUs, and TPUs
are struggling to keep up with the demands of these AI applications.
Non-coherent optical computing represents a promising approach for light-speed
acceleration of AI workloads. In this paper, we show how cross-layer design can
overcome challenges in non-coherent optical computing platforms. We describe
approaches for optical device engineering, tuning circuit enhancements, and
architectural innovations to adapt optical computing to a variety of AI
workloads. We also discuss techniques for hardware/software co-design that can
intelligently map and adapt AI software to improve its performance on
non-coherent optical computing platforms.

本文介绍了一种基于非相干光学计算平台的 AI 工作负载加速方法，通过交叉层设计，优化了非相干光学计算平台的光学器件工程、调谐电路增强和架构创新，并探讨了硬件 / 软件协同设计等技术来智能化映射和适应 AI 软件，以提高其在非相干光学计算平台上的性能。

利用非相干光计算进行 AI 加速的跨层设计

Cross-Layer Design for AI Acceleration with Non-Coherent Optical Computing

Deep Neural Networks (DNNs) are capable of solving complex problems in
domains related to embedded systems, such as image and natural language
processing. To efficiently implement DNNs on a specific FPGA platform for a
given cost criterion, e.g. energy efficiency, an enormous amount of design
parameters has to be considered from the topology down to the final hardware
implementation. Interdependencies between the different design layers have to
be taken into account and explored efficiently, making it hardly possible to
find optimized solutions manually. An automatic, holistic design approach can
improve the quality of DNN implementations on FPGA significantly. To this end,
we present a cross-layer design space exploration methodology. It comprises
optimizations starting from a hardware-aware topology search for DNNs down to
the final optimized implementation for a given FPGA platform. The methodology
is implemented in our Holistic Auto machine Learning for FPGAs (HALF)
framework, which combines an evolutionary search algorithm, various
optimization steps and a library of parametrizable hardware DNN modules. HALF
automates both the exploration process and the implementation of optimized
solutions on a target FPGA platform for various applications. We demonstrate
the performance of HALF on a medical use case for arrhythmia detection for
three different design goals, i.e. low-energy, low-power and high-throughput
respectively. Our FPGA implementation outperforms a TensorRT optimized model on
an Nvidia Jetson platform in both throughput and energy consumption.

本研究提出了一种跨层设计空间探索的自动化方法，利用 HALF 框架，结合进化搜索算法、各种最优化步骤和参数化硬件 DNN 模块的库，为嵌入式系统上的深度神经网络实现在成本标准下的优化解决方案，提升了 DNN 在 FPGA 上的性能表现，且在医疗应用的心律失常检测中，得到了较佳效果。