Training new engineers in digital design is a challenge, particularly when it
comes to teaching the complex electronic design automation (EDA) tooling used
in this domain. Learners will typically deploy designs in the Verilog and VHDL
hardware description languages to Field Programmable Gate Arrays (FPGAs) from
Altera (Intel) and Xilinx (AMD) via proprietary closed-source toolchains
(Quartus Prime and Vivado, respectively). These tools are complex and difficult
to use -- yet, as they are the tools used in industry, they are an essential
first step in this space. In this work, we examine how recent advances in
artificial intelligence may be leveraged to address aspects of this challenge.
Specifically, we investigate if Large Language Models (LLMs), which have
demonstrated text comprehension and question-answering capabilities, can be
used to generate novice-friendly explanations of compile-time synthesis error
messages from Quartus Prime and Vivado. To perform this study we generate 936
error message explanations using three OpenAI LLMs over 21 different buggy code
samples. These are then graded for relevance and correctness, and we find that
in approximately 71% of cases the LLMs give correct & complete explanations
suitable for novice learners.

通过使用大型语言模型，本研究考察了如何利用人工智能的最新进展，生成适合初学者理解的编译时综合错误消息的解释，以在数字设计中培养新工程师。

利用 LLMs 解释 EDA 综合错误

Explaining EDA synthesis errors with LLMs

In this work, we present a reinforcement learning (RL) based approach to
designing parallel prefix circuits such as adders or priority encoders that are
fundamental to high-performance digital design. Unlike prior methods, our
approach designs solutions tabula rasa purely through learning with synthesis
in the loop. We design a grid-based state-action representation and an RL
environment for constructing legal prefix circuits. Deep Convolutional RL
agents trained on this environment produce prefix adder circuits that
Pareto-dominate existing baselines with up to 16.0% and 30.2% lower area for
the same delay in the 32b and 64b settings respectively. We observe that agents
trained with open-source synthesis tools and cell library can design adder
circuits that achieve lower area and delay than commercial tool adders in an
industrial cell library.

本文提出了一种基于强化学习的方法来设计高性能数字电路中的并行前缀电路，使用深度卷积强化学习代理在环境中进行训练，设计出 Pareto 优化现有基线的前缀加法电路，其面积和时延分别比现有基线低 16.0％和 30.2％。经实验表明，训练对公开源代码进行的综合工具和电池库的代理可以设计出优于商业工具加法器的电路。