Deep neural networks (DNNs) have achieved great breakthroughs in many fields
such as image classification and natural language processing. However, the
execution of DNNs needs to conduct massive numbers of multiply-accumulate (MAC)
operations on hardware and thus incurs a large power consumption. To address
this challenge, we propose a novel digital MAC design based on encoding. In
this new design, the multipliers are replaced by simple logic gates to project
the results onto a wide bit representation. These bits carry individual
position weights, which can be trained for specific neural networks to enhance
inference accuracy. The outputs of the new multipliers are added by bit-wise
weighted accumulation and the accumulation results are compatible with existing
computing platforms accelerating neural networks with either uniform or
non-uniform quantization. Since the multiplication function is replaced by
simple logic projection, the critical paths in the resulting circuits become
much shorter. Correspondingly, pipelining stages in the MAC array can be
reduced, leading to a significantly smaller area as well as a better power
efficiency. The proposed design has been synthesized and verified by
ResNet18-Cifar10, ResNet20-Cifar100 and ResNet50-ImageNet. The experimental
results confirmed the reduction of circuit area by up to 79.63% and the
reduction of power consumption of executing DNNs by up to 70.18%, while the
accuracy of the neural networks can still be well maintained.

通过基于编码的新型数字 MAC 设计，用简单逻辑门替换了乘法器，用宽位表示投射结果，通过逐位加权累积实现加法，从而减小电路面积和提高功耗效率，测试结果表明该设计能够降低电路面积高达 79.63%，减少 DNN 执行功耗最多 70.18%，同时保持良好的神经网络准确性。