Embedded field programmable gate array (eFPGA) technology allows the
implementation of reconfigurable logic within the design of an
application-specific integrated circuit (ASIC). This approach offers the low
power and efficiency of an ASIC along with the ease of FPGA configuration,
particularly beneficial for the use case of machine learning in the data
pipeline of next-generation collider experiments. An open-source framework
called "FABulous" was used to design eFPGAs using 130 nm and 28 nm CMOS
technology nodes, which were subsequently fabricated and verified through
testing. The capability of an eFPGA to act as a front-end readout chip was
tested using simulation of high energy particles passing through a silicon
pixel sensor. A machine learning-based classifier, designed for reduction of
sensor data at the source, was synthesized and configured onto the eFPGA. A
successful proof-of-concept was demonstrated through reproduction of the
expected algorithm result on the eFPGA with perfect accuracy. Further
development of the eFPGA technology and its application to collider detector
readout is discussed.

使用嵌入式可编程门阵列（eFPGA）技术在应用特定集成电路（ASIC）的设计中实现可重构逻辑，将 ASIC 的低功耗和高效性与 FPGA 的易配置性相结合，尤其适用于下一代对撞机实验数据流中的机器学习用例。通过开源框架 “FABulous”，设计了使用 130 纳米和 28 纳米 CMOS 技术节点的 eFPGA，并经过测试进行了验证。通过模拟高能粒子经过硅像素传感器和基于机器学习的分类器的测试，验证了 eFPGA 作为前端读出芯片的能力。通过在 eFPGA 上成功合成和配置传感器数据的降维算法，以完美准确度复现了预期算法结果。讨论了对 eFPGA 技术的进一步发展以及其在对撞机探测器读出中的应用。